Receiver circuit comprising equalizer

• US 20050226355A1
• Filed: 02/04/2005
• Published: 10/13/2005
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka, Kibune, Masaya
• Granted Patent: US 7,508,892 B2
• Time in Patent Office: Days
• US Class Current: 375/348
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/0328 with interference cancellation circuitry adaptations for interference cancellation within a sequence estimator H04L25/03305; interference related aspects of direct sequence spread spectrum H04B1/7097; interference related aspects of frequency hopping spread spectrum H04B1/715; see also H04B1/10

Abstract

A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.

Claims

1. A receiver circuit for receiving a received signal that propagates through a transmission medium, comprising:

an equalizer that equalizes the received signal;

a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal;

an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal;

an equalizer characteristic control unit that controls the characteristic of the equalizer to minimize the intersymbol interference level detected by the intersymbol interference detection circuit; and

a data sample timing control unit in which the data sample timing is controlled to a minimal sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.

2. The receiver circuit according to claim 1, wherein the data sample timing control unit detects the sample timing at which the difference is minimal;

the intersymbol interference detection circuit detects the intersymbol interference level on the basis of the data sample timing that is controlled to the sample timing thus detected; and

a characteristic adjustment process, in which the equalization characteristic control unit adjusts the characteristic of the equalizer on the basis of the intersymbol interference level thus detected, is repeated.

3. The receiver device according to claim 1, wherein the intersymbol interference detection circuit further detects a second intersymbol interference level at a second data sample timing at which the phase lags behind or lies in advance of the phase at the data sample timing corresponding with the minimum sample timing;

and

the equalization characteristic control unit controls the characteristic of the equalizer to reduce the second intersymbol interference level.

4. The receiver circuit according to claim 3, wherein the equalization characteristic control unit controls the characteristic of the equalizer to reduce an added intersymbol interference level that is rendered by adding, on the basis of predetermined weighting, the intersymbol interference level at the minimum sample timing and the second intersymbol interference level.

5. A receiver circuit for receiving a received signal that propagates through a transmission medium, comprising:

an equalizer that equalizes the received signal;

a data detection circuit that detects, at a data sample timing, an analog output signal of the equalizer and outputs a digital signal; and

an equalization characteristic control unit that detects a phase fluctuation amount at the data boundary of the analog output signal of the equalizer and controls the characteristic of the equalizer to reduce the phase fluctuation amount at the data boundary.

6. The receiver circuit according to claim 5, wherein the equalization characteristic control unit detects the amplitude of the analog output signal at the boundary timing for each combination data of the digital signal of the data detection circuit and detects the phase fluctuation amount at the data boundary in accordance with the amplitude thus detected.

7. The receiver circuit according to claim 6, wherein the equalization characteristic control unit integrates the amplitudes detected for each of the combination data a plurality of times and detects the phase fluctuation amount at the data boundary in accordance with the maximum value of the amplitudes thus integrated.

8. The receiver circuit according to claim 6, wherein the equalization characteristic control unit controls the characteristic of the equalizer so that the phase fluctuation amount at the data boundary corresponding with all the combination data found in accordance with the amplitudes detected for each combination data is less than a predetermined threshold value.

9. The receiver circuit according to claim 5, wherein the equalization characteristic control unit detects the sample timing at which the first and second amplitudes corresponding with first and second combination data, which are amplitudes of the analog output signal to be sampled in correspondence with the combination data items of the digital signal of the data detection circuit, are distinguishable, and detects the phase fluctuation amount at the data boundary in accordance with the difference between the boundary timing and the detected sample timing.

10. The receiver circuit according to claim 9, wherein the equalization characteristic control unit detects the sample timing at which the first and second amplitudes are distinguishable by scanning the sample timings with the boundary timing serving as the starting point.

11. A receiver circuit for receiving a received signal that propagates through a transmission medium, comprising:

an equalizer that equalizes the received signal;

a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; and

an equalization characteristic control unit that detects the amplitude fluctuation amount at the data boundary of the analog output signal of the equalizer and controls the characteristic of the equalizer to reduce the amplitude fluctuation amount at the data boundary.

12. The receiver circuit according to claim 11, further comprising:

a boundary timing detection unit that detects the amplitude of the analog output signal at the sample timing when the digital signal of the data detection circuit undergoes a data transition and detects the sample timing at which the detected amplitude is minimal, wherein the equalization characteristic control unit detects the amplitude fluctuation amount at the data boundary in accordance with the amplitude of the analog output signal at the sample timing detected by the boundary timing detection unit.

13. The receiver circuit according to claim 12, wherein the boundary timing detection unit integrates the absolute values of the amplitude of the analog output signal and detects the sample timing at which the integral value is a minimum value.