Method for fabricating semiconductor devices using strained silicon bearing material

• US 20050227425A1
• Filed: 06/09/2005
• Published: 10/13/2005
• Est. Priority Date: 11/18/2003
• Status: Active Grant

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J.
• Granted Patent: US 7,462,526 B2
• Time in Patent Office: Days
• US Class Current: 438/198
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of manufacturing an integrated circuit on semiconductor substrates, e.g., silicon wafer. The method includes providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing. In a specific embodiment, the semiconductor substrate has an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing. The method patterns a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material. In a preferred embodiment, the patterns are made using a masking and etching process.

Claims

1. A method of manufacturing an integrated circuit on semiconductor substrates, the method comprising:

providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing, the semiconductor substrate having an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a first tensile mode and/or compressive mode along the film surface crystal axes across a portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing; and

patterning a predetermined region in a portion of the film of material to cause the first tensile mode to change to a second tensile mode in the patterned predetermined region if the portion of the film of material is in the first tensile mode or to cause the first compressive mode to change to a second compressive mode in a patterned predetermine region if the portion of the film of material is in the first compressive mode.

2. The method of claim 1 wherein the second spacing places the film of material in the tensile mode.

3. The method of claim 1 wherein the second spacing places the film of material in the compressive mode.

4. The method of claim 1 wherein the processing of the predetermined region comprises:

forming a masking layer overlying the film of material; and

etching the portion of the film of material to form the predetermined region.

5. The method of claim 4 wherein the etching comprises a wet etching process.

6. The method of claim 4 wherein the predetermined region comprises an exposed portion of the film of material.

7. The method of claim 1 wherein the predetermined region comprises an unexposed portion of the film of material.

8. The method of claim 1 wherein the film of material is strained silicon bearing material.

9. The method of claim 8 wherein the strained silicon bearing material is overlying an epitaxial silicon-germanium material, the epitaxial silicon-germanium material overlying the semiconductor substrate.

10. The method of claim 1 wherein the patterning of the predetermined region comprises a dry etching process.

11. The method of claim 1 wherein the patterning of the predetermined region comprises masking and dry etching.

12. The method of claim 1 wherein the first lattice structure is for a lattice structure for a silicon substrate and the second lattice structure is for a strained silicon material.

13. The method of claim 12 further comprising forming an insulating material overlying the semiconductor substrate, the insulating material being between the semiconductor substrate and the film of material.

14. The method of claim 13 wherein the film of material consisting of strained silicon bearing material is overlying an epitaxial silicon-germanium material.

15. The method of claim 1 wherein the first tensile and/or compressive mode is characterized by a uniaxial strain characteristic.

16. The method of claim 1 wherein the first tensile or compressive mode is characterized by a biaxial strain characteristic.

17. The method of claim 1 wherein the second compressive mode is characterized by a second strain value that has a higher absolute value than a first strain value of the first compressive mode.

18. The method of claim 1 wherein the second tensile mode is characterized by a second strain value that has a higher absolute value than a first strain value of the first tensile mode.

19. The method of claim 1 wherein the second compressive mode is characterized by a second strain value that has a higher real value than a first strain value of the first compressive mode.

20. The method of claim 1 wherein the second tensile mode is characterized by a second strain value that has a higher real value than a first strain value of the first tensile mode.

21. The method of claim 1 wherein the predetermined region is for a channel region of a transistor for a microprocessor device or a memory device or a logic device.

22. The method of claim 1 wherein the predetermined region is for a channel region having a channel length in a direction of a <

110>

crystal direction of the semiconductor substrate.

23. The method of claim 1 wherein the predetermined region is for a channel region having a channel length in an orthogonal direction of a <

110>

crystal direction of the semiconductor substrate.

24. The method of claim 1 wherein the predetermined region is for a channel region having a channel length in a <

111>

crystal direction of the semiconductor substrate.

25. The method of claim 1 wherein the predetermined region is for a channel region having a channel length in a <

100>

crystal direction of the semiconductor substrate.

26. A method of manufacturing an integrated circuit on semiconductor substrates, the method comprising:

providing a semiconductor substrate characterized by a first lattice with a first structure and a first spacing, the semiconductor substrate having an overlying film of material with a second lattice with a second structure and a second spacing, the second spacing placing the film of material in a strain mode characterized by a first tensile and/or compressive mode along a single film surface crystal axis across a first portion of the film of material relative to the semiconductor substrate with the first structure and the first spacing; and

patterning a predetermined region of the first portion of the film of material to cause the first tensile and/or compressive mode in the first portion of the film of material to change to a second tensile and/or compressive mode in a resulting patterned portion of the first portion of the film of material.

27. The method of claim 26 wherein the portion of the film is an entirety of the film.

28. The method of claim 26 wherein the portion of the film is an entirety of a thickness of the film.