Method of fabricating self-aligned source and drain contacts in a double gate fet with controlled manufacturing of a thin Si or non-Si channel

• US 20050227444A1
• Filed: 03/28/2005
• Published: 10/13/2005
• Est. Priority Date: 03/29/2004
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Gerarda Petra Loo, Josine Johanna, Ponomarev, Youri V.
• Granted Patent: US 7,795,112 B2
• Time in Patent Office: Days
• US Class Current: 438/289
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Claims

1. A method of forming a transistor structure on a substrate comprising a supporting Si layer, a buried insulating layer, and a top Si layer, the method comprising:

forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level;

forming an open area on the top Si layer demarcated by at least one of a demarcating oxide and a resist layer region;

forming high level impurity or heavily-damaged regions by ion implantation so that the open area is exposed to an ion beam wherein the demarcating layer region and the gate region act as an implantation mask, wherein the ion beam comprises a combination of a beam energy and a dose, thereby enabling formation in the top Si layer of high impurity level regions below the source and drain regions in the buried insulating layer and of a high impurity level or heavily-damaged region below the gate region in the top Si layer.

2. The method of forming a transistor structure according to claim 1, further comprising:

forming a silicon dioxide capping layer;

wafer bonding the substrate to a second substrate, wherein the second substrate comprises a silicon dioxide top layer, and wherein the capping layer is face-to-face with the silicon dioxide top layer.

3. The method of forming a transistor structure according to claim 1, further comprising:

initially removing the Si support layer using the buried insulating layer as a stopping layer;

further removing the buried insulating layer using the top Si layer as a stopping layer.

4. The method of forming a transistor structure according to claim 3, further comprising:

removing the high impurity level region of the top Si layer below the gate region by selective etching using the source and drain regions as a stopping layer, thereby creating a gap between the source and drain regions.

5. The method of forming a transistor structure according to claim 4, further comprising using one of the dielectric region and the gate region as an additional stopping layer for removing the high impurity level region of the top Si layer below the gate region.

6. The method of forming a transistor structure according to claim 4, further comprising depositing a channel layer in the gap to form a channel region.

7. The method of forming a transistor structure according to claim 6, wherein the channel layer comprises as channel material at least one of the following:

a semiconductor material including one of Si, SiGe, Ge, GaAs, and InP, a III-V compound, a II-VI compound, a metal, an intermetallic compound, an organic compound, and a bio-organic compound.

8. The method of forming a transistor structure according to claim 6, wherein the channel layer comprises one of a quantum wire structure and a quantum dot structure.

9. The method of forming a transistor structure according to claim 8, wherein the channel layer comprises one of nano-wires, an array of nano-dots, carbon nano-dots, and nano-tubes.

10. The method of forming a transistor structure according to claim 1, wherein the ion beam comprises ions of one of Ge, I, and Br.

11. The method of forming a transistor structure according claim 1, wherein the transistor structure is a MOSFET structure.

12. The method of forming a transistor structure according to claim 1, wherein the transistor structure is a bipolar structure, wherein the gate is arranged as an emitter, wherein the channel region is arranged as a collector, wherein the gate dielectric is arranged as a base, and wherein the self-aligned source and drain regions are arranged as contacts to the base.

13. A transistor structure on a substrate, comprising a gate region, and a source and drain region, wherein the transistor structure is fabricated according to the method of claim 1.

14. A semiconductor device comprising a transistor structure in accordance with claim 13.