Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture

• US 20050228606A1
• Filed: 06/10/2005
• Published: 10/13/2005
• Est. Priority Date: 02/26/1997
• Status: Active Grant

• Current Assignee: Raymond J. Beffa
• Original Assignee: Raymond J. Beffa
• Inventors: Beffa, Raymond J.
• Granted Patent: US 7,124,050 B2
• Time in Patent Office: Days
• US Class Current: 702/119
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: H01L 21/67294 using identification means, e.g. labels on substrates or labels on containers
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is stored in each IC, and an electronic wafer map is electronically stored for each wafer indicating the locations of good and bad ICs on the wafer and the fuse IDs of the ICs on the wafer. Each IC is then separated from its wafer to form an IC die, and the IC dice are assembled into IC devices. At the opens/shorts test at the end of assembly, the fuse ID of each IC in each device is automatically retrieved so the wafer map of the IC device may be accessed and evaluated to identify any IC devices containing bad ICs that have accidentally been assembled into IC devices. Any “bad” IC devices are discarded while remaining IC devices continue on to back-end testing.

Claims

1. A manufacturing process having data for integrated circuit devices manufactured during said process comprising:

storing data and a substantially unique identification code for each integrated circuit device of the integrated circuit devices at either probe testing of the integrated circuit devices or thereafter, the data indicating a process flow within the manufacturing process for each integrated circuit device of the integrated circuit devices, storing data comprising;

storing the substantially unique identification code of each integrated circuit device of the integrated circuit devices and a die location on an electronically stored wafer map for each integrated circuit device;

reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices for evaluating the data for each integrated circuit device of the integrated circuit devices to the data for manufacturing process data stored for each integrated circuit device for identifying integrated circuit devices having a process flow within the manufacturing process different from the process flow of the data stored of the integrated circuit devices; and

directing the integrated circuit devices identified as having a process flow within the manufacturing process different from the process flow of the data stored of the integrated circuit devices to another process.

2. The process of claim 1, wherein storing data comprises storing data at a probe.

3. The process of claim 1, wherein storing data comprises storing data and the substantially unique identification code of each integrated circuit device of the integrated circuit devices to indicate each integrated circuit device of the integrated circuit devices comprises one of a good integrated circuit device and a bad integrated circuit device.

4. The process of claim 1, wherein reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices comprises electrically retrieving a unique fuse identification programmed into each integrated circuit device of the integrated circuit devices.

5. The process of claim 1, wherein reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices comprises optically reading a unique identification code on each integrated circuit device of the integrated circuit devices.

6. The process of claim 5, wherein optically reading the unique identification code on each integrated circuit device of the integrated circuit devices comprises optically reading a unique laser fuse identification programmed into each integrated circuit device of the integrated circuit devices.

7. The process of claim 1, wherein reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices comprises reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices at an opens/shorts test in the manufacturing process.

8. The process of claim 1, wherein the stored data and the substantially unique identification code of each integrated circuit device of the integrated circuit devices are accessed by accessing the stored data and the substantially unique identification code of each integrated circuit device of the integrated circuit devices at an opens/shorts test in the manufacturing process.

9. The process of claim 8, wherein evaluating the data comprises evaluating the data for each integrated circuit device of the integrated circuit devices to identify any bad integrated circuit devices having undergone an assembly procedure within the manufacturing process.

10. The process of claim 9, wherein evaluating the data comprises evaluating the data at an opens/shorts test in the manufacturing process.

11. The process of claim 1, wherein directing the integrated circuit devices identified as having a process flow within the manufacturing process different from the process flow of the stored data of the integrated circuit devices to another process comprises discarding any integrated circuit device identified as having a process flow within the manufacturing process different from the process flow of the stored data.

12. The process of claim 1, wherein directing occurs before a back-end test procedure within the manufacturing process.

13. The process of claim 1, further comprising assembling the integrated circuit devices into packaged integrated circuit devices after storing data and before reading the substantially unique identification code of each integrated circuit device of the integrated circuit devices.

14. A method of manufacturing integrated circuit devices using a plurality of semiconductor wafers, each wafer having a plurality of integrated circuit devices thereon comprising:

providing integrated circuit devices selected from a group comprising Dynamic Random Access Memory (DRAM) devices, Static Random Access Memory (SRAM) devices, synchronous DRAM (SDRAM) devices, and processor devices;

storing a substantially unique identification code in each integrated circuit device of the plurality of integrated circuit devices on each semiconductor wafer of the plurality of semiconductor wafers;

storing data and the substantially unique identification code of each integrated circuit device of the plurality of integrated circuit devices indicating each manufacturing process for each integrated circuit device of the plurality of integrated circuit devices at one of probe testing and after probe testing of the plurality of integrated circuit devices;

assembling each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device assembly;

reading the substantially unique identification code of each integrated circuit device of the integrated circuit device assemblies;

determining for each integrated circuit device of the integrated circuit device assemblies any integrated circuit devices having undergone any manufacturing process different from the indicated manufacturing processes of the stored data for each integrated circuit device;

subjecting to further processing the integrated circuit devices of the plurality of integrated circuit devices identified as having undergone a manufacturing process different from the indicated manufacturing processes of its stored data; and

back-end testing integrated circuit devices not subjected to further processing.

15. The method of claim 14, further comprising programming each integrated circuit device of the plurality of integrated circuit devices on each semiconductor wafer of the plurality of semiconductor wafers to permanently store a unique fuse identification.

16. The method of claim 15, wherein programming each integrated circuit device of the plurality of integrated circuit devices on each semiconductor wafer of the plurality of semiconductor wafers to permanently store the unique fuse identification comprises programming at least one of fuses and anti-fuses in each integrated circuit device of the plurality of integrated circuit devices on each semiconductor wafer of the plurality of semiconductor wafers to permanently store the unique fuse identification.

17. The method of claim 14, wherein assembling each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device assembly comprises:

picking each integrated circuit device of the plurality of integrated circuit devices from its semiconductor wafer of the plurality of semiconductor wafers;

placing each integrated circuit device of the plurality of integrated circuit devices onto an epoxy-coated bonding site of one of a plurality of lead frames;

curing the epoxy on the bonding site of each one of the plurality of lead frames;

wire bonding each integrated circuit device of the plurality of integrated circuit devices to its associated lead frame;

injection molding each integrated circuit device of the plurality of integrated circuit devices and its associated lead frame to form one of a plurality of integrated circuit device packages, each having projecting leads;

deflashing the projecting leads of each integrated circuit device package of the plurality of integrated circuit device packages;

curing each integrated circuit device package of the plurality of integrated circuit device packages;

electroplating the projecting leads of each integrated circuit device package of the plurality of integrated circuit device packages;

singulating each integrated circuit device package of the plurality of integrated circuit device packages into one of a plurality of discrete integrated circuit devices; and

testing each discrete integrated circuit device of the plurality of discrete integrated circuit devices for opens and shorts.

18. The method of claim 14, wherein assembling each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device assembly comprises assembling each integrated circuit device of the plurality of integrated circuit devices into an integrated circuit device selected from a group comprising a wire bond/lead frame integrated circuit device, a Chip-On-Board (COB) integrated circuit device, a flip-chip integrated circuit device, and a Tape-Automated Bonding (TAB) integrated circuit device.

19. A Multi-Chip Module manufacturing process using a plurality of integrated circuit devices from at least one semiconductor wafer comprising:

storing a substantially unique identification code in each integrated circuit device of the plurality of integrated circuit devices on the semiconductor wafer at one of probe testing and after probe testing;

storing data and the substantially unique identification code of each integrated circuit device of the plurality of integrated circuit devices indicating desired manufacturing processes for each integrated circuit device of the plurality of integrated circuit devices;

assembling one or more integrated circuit devices of the plurality of integrated circuit devices into each of a plurality of multi-chip modules, the plurality of multi-chip modules selected from a group comprising Single In-Line Memory Modules (SIMM'"'"'s) and Dual In-line Memory Modules (DIMM'"'"'s);

reading the substantially unique identification code of each integrated circuit device of the plurality of integrated circuit devices in each of the plurality of multi-chip modules;

evaluating data for each integrated circuit device of the plurality of integrated circuit devices in each of the plurality of multi-chip modules identifying any multi-chip modules having integrated circuit devices having undergone a manufacturing process that is different from the desired manufacturing processes;

redirecting any multi-chip modules identified as having integrated circuit devices having undergone the manufacturing process that is different from the desired manufacturing processes; and

back-end testing any nonredirected multi-chip modules.