Local preferred direction architecture, tools, and apparatus

• US 20050229134A1
• Filed: 12/06/2004
• Published: 10/13/2005
• Est. Priority Date: 12/07/2000
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fujimura, Akira, King, Roger, Hetzel, Asmus, Jacques, Etienne, Malhotra, Anish, Matveev, Alexandre, Frankle, Jon, Harrison, David S., Feather, Heath
• Granted Patent: US 7,441,220 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different preferred direction than the particular wiring layer. In addition, each region has a local preferred direction that differs from the local preferred direction of at least one other region in the set. Furthermore, at least two regions have two different polygonal shapes and no region in the set encompasses another region in the set. Some embodiments also provide a Graphical User Interface (GUI) that facilitates a visual presentation of an LPD design layout and provides tools to create and manipulate LPD regions in a design layout.

Claims

1. A design layout comprising:

(a) a plurality of wiring layers; and

(b) a set of polygonally shaped regions on one of the layers, each region in the set having a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different polygonal shapes,

(c) wherein no region in the set encompasses another region in the set.

2. The layout of claim 1, wherein the plurality of regions comprise:

(a) a first region in the shape of a quadrilateral polygon; and

(b) a second region in the shape of a quadrilateral polygon.

3. The layout of claim 1, wherein the plurality of regions comprise:

(a) a first region in the shape of a non-quadrilateral polygon; and

(b) a second region in the shape of a non-quadrilateral polygon.

4. The layout of claim 1, wherein the plurality of regions comprise:

(a) a first region in the shape of a quadrilateral polygon; and

(b) a second region in the shape of a non-quadrilateral polygon.

5. The layout of claim 4, wherein the second region is in the shape of an octagon.

6. The layout of claim 4, wherein the second region is in the shape of a hexagon.

7. The layout of claim 1, wherein the plurality of regions comprise at least two regions that have a Manhattan local preferred wiring direction.

8. The layout of claim 1, wherein the plurality of regions comprise at least two regions that have a diagonal local preferred wiring direction.

9. The layout of claim 8, wherein the diagonal local preferred wiring directions are orthogonal to each other.

10. The layout of claim 8, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.

11. The layout of claim 1, wherein the plurality of regions comprise at least one region that has a Manhattan local preferred wiring direction and at least one region that has a diagonal local preferred wiring direction.

12. A design layout comprising:

(a) a plurality of wiring layers; and

(b) a set of regions on one of the layers, each region in the set having a polygonal shape and a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different polygonal shapes, wherein each polygonal shape is a convex polygon.

13. A multi-layer design layout comprising:

(a) a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and

(b) a second wiring layer positioned directly above or below said first wiring layer, wherein said second wiring layer has at least one region above or below said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one pre-designed circuit block,

(c) wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.

14. The multi-layer design layout of claim 13, wherein said second wiring layer has a diagonal preferred wiring direction.

15. The multi-layer design layout of claim 14, wherein said at least one region has a Manhattan local preferred wiring direction.

16. The multi-layer design layout of claim 13, wherein a pre-designed circuit block is an IP block.

17. A multi-layer design layout comprising:

(a) a first wiring layer with first and second regions with different local preferred wiring directions;

(b) a second wiring layer with third and fourth regions with different local preferred wiring directions;

(c) a first via between the first and third regions;

(d) a second via between the second and fourth regions;

wherein the shape of the first and second vias differ.

18. The multi-layer design layout of claim 17, wherein each via has two via pads, wherein the shape of the first and second vias differ since the shape of at least one of the via pads of one of the vias is different than the shape of both the via pads of the other via.

19. A design layout comprising:

(a) at least two regions having different preferred wiring directions; and

(b) at least one boundary region shared between the two regions,

(c) wherein said boundary region is not parallel to either one of the preferred wiring directions of the two regions.

20. A design layout comprising:

(a) a wiring layer;

(b) a first block on said wiring layer, said first block having a local preferred wiring direction on the wiring layer that is different than another local preferred wiring direction on the wiring layer; and

(c) a region encompassing said first block, wherein said region has a local preferred wiring direction that is parallel to the local preferred wiring direction of said first block.

21. The design layout of claim 20 further comprising a second block positioned on said wiring layer, said second block having a local preferred wiring direction parallel to the preferred wiring direction of the first block, wherein said region encompasses both said first and second blocks.

22. The design layout of claim 21, wherein the blocks are part of a power stripe.

23. The design layout of claim 22, wherein the other preferred wiring direction of the wiring layer is a diagonal preferred wiring direction.

24. The design layout 22, wherein the blocks are pre-designed circuit blocks.

25. The design layout of claim 24, wherein the circuit blocks are memory arrays.

26. The design layout 24, wherein the circuit block are IP blocks.

27. A graphical user interface comprising:

(a) a design window that illustrates a design layout with plurality of wiring layers;

(b) a set of at least two regions with different local preferred wiring directions on one wiring layer in the layout;

(c) a set of graphical indicators illustrating the preferred wiring direction of each region in the set of regions.

28. The graphical user interface of claim 27, wherein, in the graphical user interface, said graphical indicators are selectable objects for selecting and moving to redefine the preferred wiring directions of the region.

29. The graphical user interface of claim 27, wherein said graphical indicators are arrows.

30. The graphical user interface of claim 27, wherein at least two regions have different polygonal shapes.

31. The graphical user interface of claim 27, wherein the set of graphical indicators is a first set of graphical indicators, wherein the graphical user interface further comprising a second set of graphical indicators that identify edges of regions that are impermeable to wiring.

32. An integrated circuit (“

IC”

) comprising;

(a) a plurality of wiring layers; and

(b) a set of regions on one of the layers, each region in the set having a shape and a local preferred wiring direction that is different than the local preferred wiring direction of at least one other region in the set, wherein at least two regions have two different shapes,

(c) wherein no region in the set encompasses another region in the set.

33. The IC of claim 32, wherein the plurality of regions comprise:

(a) a first region in the shape of a quadrilateral polygon; and

(b) a second region in the shape of a quadrilateral polygon.

34. The IC of claim 32, wherein the plurality of regions comprise:

(a) a first region in the shape of a non-quadrilateral polygon; and

(b) a second region in the shape of a non-quadrilateral polygon.

35. The IC of claim 32, wherein the plurality of regions comprise:

(a) a first region in the shape of a quadrilateral polygon; and

(b) a second region in the shape of a non-quadrilateral polygon.

36. The IC of claim 32, wherein the plurality of regions comprise at least two regions that have a Manhattan local preferred wiring direction.

37. The IC of claim 32, wherein the plurality of regions comprise at least two regions that have a diagonal local preferred wiring direction.

38. The IC of claim 32, wherein the diagonal local preferred wiring directions are orthogonal to each other.

39. The IC of claim 38, wherein the diagonal local preferred wiring directions are neither parallel nor orthogonal to each other.

40. The IC of claim 32, wherein the plurality of regions comprise at least one region that has a Manhattan local preferred wiring direction and at least one region that has a diagonal local preferred wiring direction.

41. A multi-layer integrated circuit comprising:

(a) a first wiring layer having at least one pre-designed circuit block having a preferred wiring direction; and

(b) a second wiring layer positioned directly above or below said first wiring layer, wherein said second wiring layer has at least one region above or below said pre-designed circuit block, said region having a local preferred wiring direction parallel or orthogonal to the preferred wiring direction of said at least one pre-designed circuit block,

(c) wherein the local preferred wiring direction of the region is different than a preferred wiring direction of at least one other region on the second wiring layer.

42. The multi-layer IC of claim 41, wherein said second wiring layer has a diagonal preferred wiring direction.

43. The multi-layer design layout of claim 42, wherein said at least one region has a Manhattan local preferred wiring direction.

44. The multi-layer design layout of claim 41, wherein a pre-designed circuit block is an IP block.

45. An integrated circuit comprising:

(a) at least two regions having different preferred wiring directions; and

(b) at least one boundary region shared between the two regions,

(c) wherein said boundary region is not parallel to either one of the preferred wiring directions of the two regions.

46. An integrated circuit (“

IC”

) comprising;

(a) a wiring layer;

(b) a first block on said wiring layer, said first block having a local preferred wiring direction on the wiring layer that is different than another local preferred wiring direction on the wiring layer; and

(c) a region encompassing said first block, wherein said region has a local preferred wiring direction that is parallel to the local preferred wiring direction of said first block.

47. The IC of claim 46 further comprising a second block positioned on said wiring layer, said second block having a local preferred wiring direction parallel to the preferred wiring direction of the first block, wherein said region encompasses both said first and second blocks.

48. The IC of claim 47, wherein the blocks are part of a power stripe.

49. The IC of claim 48, wherein the other preferred wiring direction of the wiring layer is a diagonal preferred wiring direction.

50. The IC 46, wherein the blocks are pre-designed circuit blocks.

51. The IC of claim 50, wherein the circuit blocks are memory arrays.

52. The IC of claim 50, wherein the circuit block are IP blocks.