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High performance system-on-chip discrete components using post passivation process

  • US 20050230783A1
  • Filed: 02/18/2005
  • Published: 10/20/2005
  • Est. Priority Date: 12/21/1998
  • Status: Active Grant
First Claim
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1. A post passivation system, comprising:

  • a semiconductor substrate, having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over the at least one interconnect metal layer, wherein the passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;

    a post-passivation metal layer contacting said at least one top level metal contact point through said at least one passivation opening; and

    a discrete component, overlying and connected to said post-passivation metal layer;

    wherein said passivation opening'"'"'s width is larger than about 0.1 μ

    m.

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