Apparatus and method for detecting photon emissions from transistors

• US 20050231219A1
• Filed: 03/02/2005
• Published: 10/20/2005
• Est. Priority Date: 09/03/2002
• Status: Active Grant

• Current Assignee: DCG Systems Incorporated (Thermo Fisher Scientific Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Lundquist, Theodore R., Perdu, Philippe, Desplats, Romain, Shah, Ketan J.
• Granted Patent: US 7,400,154 B2
• Time in Patent Office: Days
• US Class Current: 324/762.20
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence

Abstract

A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.

Claims

1. A method of processing an integrated circuit CAD database for use in testing the integrated circuit with an imaging optical detector comprising:

identifying the location of at least one transistor in the integrated circuit CAD database; and

processing the integrated circuit CAD database to define at least one photon detection location as a function of the location of the at least one transistor.

2. The method of claim 1 wherein the operation of identifying the locations of the at least one transistor in the integrated circuit CAD database comprises identifying a location of a gate associated with the at least one transistor.

3. The method of claim 2 wherein the operation of identifying the locations of transistors in the integrated circuit CAD database comprises identifying the location of a source associated with the at least one transistor.

4. The method of claim 3 wherein the operation of identifying the locations of transistors in the integrated circuit CAD database comprises identifying the location of a drain associated with the at least one transistor.

5. The method of claim 4 wherein the operation of defining at least one photon detection location as a function of the locations of the at least one transistor comprises defining at least one photon detection location as a function of the location the gate, the drain, and the source or the at least one transistor.

6. The method of claim 5 wherein the at least one transistor is a PMOS transistor.

7. The method of claim 6 wherein the at least one transistor is a NMOS transistor.

8. The method of claim 7 further comprising:

identifying whether the at least one photon detection location is associated with the PMOS or the NMOS transistor.

9. The method of claim 8 wherein the operation of identifying the location of the at least one transistor in the integrated circuit CAD database is performed using at least one Boolean operation.

10. The method of claim 8 wherein the integrated circuit CAD database information comprises an identification of a NMOS gate, a NMOS drain, and a NMOS source.

11. The method of claim 10 wherein the NMOS gate information includes a polysilicon polygon layer and a P substrate polygon layer, the NMOS drain information includes an N diffusion polygon layer and a P substrate polygon layer, and the NMOS source layer includes an N diffusion polygon layer and a P substrate polygon layer.

12. The method of claim 11 wherein the operation of identifying the location of the at least one transistor in the integrated circuit CAD database is performed using at least one Boolean operation further includes the operation of applying at least one Boolean operation to the NMOS gate information.

13. The method of claim 12 wherein the at least one Boolean operation comprises:

NMOS gate=Polysilicon polygon layer AND Psubstrate polygon layer; and

NMOS Drain and Source=Ndiffusion polygon layer AND Psubstrate polygon layer.

14. The method of claim 13 further comprising:

generating a CAD file with NMOS layer information as a function of the at least one Boolean operation.

15. The method of claim 7 wherein the integrated circuit CAD database information further comprises an identification of a PMOS gate, a PMOS drain, and a PMOS source.

16. The method of claim 15 wherein the PMOS gate information includes a polysilicon polygon layer and an Nwell polygon layer, the PMOS drain information includes a Pdiffusion polygon layer and a Nwell polygon layer, and the NMOS source layer includes an Pdiffusion polygon layer and a Nwell polygon layer.

17. The method of claim 16 wherein the operation of identifying the location of the at least one transistor in the integrated circuit CAD database is performed using at least one Boolean operation further includes the operation of applying the at least one Boolean operation to the PMOS gate information.

20. The method of claim 1 wherein the at least one photon detection location comprises a generally rectangular photon emission detection window.

21. The method of claim 20 wherein the generally rectangular window defines an area associated with at least a portion of a gate region of a MOS transistor.

22. The method of claim 21 wherein the generally rectangular window further defines an area associated with at least a portion of the gate region of a MOS transistor and an adjacent pinch-off region.

23. The method of claim 22 further comprising scaling the generally rectangular window.

24. The method of claim 23 wherein the generally rectangular window is scaled in the range of between about 2 microns and about 3 microns.

25. The method of claim 24 wherein the generally rectangular window is symmetrically scaled.

26. The method of claim 25 wherein the generally rectangular window is scaled-up as a function of a thickness of the substrate of the integrated circuit.

27. The method of claim 26 wherein the generally rectangular window is scaled-up or scaled-down as a function of a separation distance of the at least one transistor.

28. The method of claim 1 further comprising:

characterizing the operation of an integrated circuit as a function of the at least one photon detection location.

29. The method of claim 28 further comprising:

testing the integrated circuit with an optical detector comprising;

obtaining an image of the integrated circuit;

aligning the image with the CAD database information for the integrated circuit;

aligning the at least one photon detection location with the location of the at least one transistor; and

detecting photon emission in the at least one photon detection location during operation of the integrated circuit.

30. The method of claim 29 further comprising:

examining photon emissions in the at least one photon detection location.

31. The method of claim 30 further comprising:

obtaining photon emissions during operation of the integrated circuit in a test loop.

32. The method of claim 29 wherein the optical detector comprises an imaging optical detector.

33. The method of claim 32 wherein the imaging optical detector comprises a picosecond imaging circuit analysis detector.

34. The method of claim 31 further comprising:

comparing the photon emissions detected in the at least one photon detection location during operation of the integrated circuit with at least one expected result.

35. The method of claim 34 wherein the operation of comparing the photon emissions detected in the at least one photon detection location during operation of the integrated circuit with at least one expected result further comprises determining faults and defects of the integrated circuit.

36. The method of claim 34 wherein the operation of comparing the photon emissions detected in the at least one photon detection location during operation of the integrated circuit with at least one expected result further comprises debugging the design of the integrated circuit.

37. The method of claim 34 wherein the operation of comparing the photon emissions detected in the at least one photon detection location during operation of the integrated circuit with at least one expected result further comprises separating design errors and process defects.

38. The method of claim 34 wherein the operation of comparing the photon emissions detected in the at least one photon detection location during operation of the integrated circuit with at least one expected result further comprises identifying an inaccurate model of the integrated circuit.

18. The method of claim 18 wherein the at least one Boolean operation comprises:

PMOS gate=Polysilicon polygon layer AND Nwell polygon layer; and

PMOS Drain and Source=Pdiffusion polygon layer AND Nwell polygon layer.

19. The method of claim 18 further comprising:

generating a CAD file with NMOS layer information as a function of the at least one Boolean operation.