System and method for dynamically varying a clock signal
First Claim
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1. A circuit comprising:
- at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit.
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Abstract
According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.
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Citations
34 Claims
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1. A circuit comprising:
at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. Voltage-to-frequency conversion circuitry comprising:
at least one delay element that receives a clock signal and outputs a delayed clock signal having an amount of delay relative to the received clock signal, said at least one delay element including a transfer gate to which either a fixed voltage supply or a variable voltage supply is provided based on the value of a track signal, wherein if the variable voltage supply is provided to said transfer gate, the transfer gate varies the amount of said delay of the delayed clock signal responsive to changes in the variable voltage supply. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A method comprising:
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receiving a first phase of a chip'"'"'s clock signal into a delay line circuit of the chip;
generating with at least one delay element of the delay line circuit a delayed clock signal having a phase that is delayed relative to the first phase of the received clock signal;
comparing with comparison circuitry on the chip the generated delayed clock signal with a later phase of the chip'"'"'s clock signal, the later phase of the chip'"'"'s clock signal being later than the first phase of the chip'"'"'s clock signal; and
determining with clock control circuitry on the chip whether to change the frequency of the chip'"'"'s clock signal, based at least in part on the comparison of the generated delayed clock signal with the later phase of the chip'"'"'s clock signal. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A method comprising:
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observing with on-chip circuitry an operating voltage of a chip; and
receiving a clock signal and generating a delayed clock signal having a delayed amount relative to the received clock signal with on-chip circuitry, wherein said delayed amount is programmatically selectable to vary responsive to changes in the observed operating voltage. - View Dependent Claims (29, 30)
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31. A method comprising:
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fabricating a chip that includes clock management circuitry for dynamically managing a clock signal of the chip responsive to observed changes in a variable operating voltage of the chip; and
programming the clock management circuitry on the fabricated chip to tailor its sensitivity to said observed changes in the chip'"'"'s variable operating voltage. - View Dependent Claims (32, 33, 34)
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Specification