System and method for dynamically varying a clock signal

• US 20050231259A1
• Filed: 06/17/2005
• Published: 10/20/2005
• Est. Priority Date: 11/07/2003
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Benjamin J. Patella, Eric S. Fetzer, Samuel D. Naffziger
• Inventors: Naffziger, Samuel D., Fetzer, Eric S., Patella, Benjamin J.
• Granted Patent: US 7,394,301 B2
• Time in Patent Office: Days
• US Class Current: 327/261
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Claims

1. A circuit comprising:

at least one delay element that is operable to receive a clock signal and generate a delayed clock signal having an amount of delay that varies based on an observed value of an operating voltage of said circuit.

2. The circuit of claim 1 further comprising:

clock control circuitry operable to dynamically control the frequency of the clock signal based at least in part on the delayed clock signal.

3. The circuit of claim 1 further comprising:

comparator circuitry for comparing a received clock signal with a generated delayed clock signal.

4. The circuit of claim 3 further comprising:

clock control circuitry operable to dynamically control the frequency of the clock signal based at least in part on the comparison of the received clock signal with a generated delayed clock signal.

5. The circuit of claim 1 comprising a plurality of delay elements and further comprising:

at least a first number of the delay elements that generate a first delayed signal having a first amount of delay relative to the received clock signal; and

at least a second number of the delay elements that generate a second delayed signal having a second amount of delay relative to the received clock signal; and

delay control circuitry operable to select either of said first or second delayed signals as said delayed clock signal.

6. The circuit of claim 5 further comprising:

a multiplexer that receives as input said first delayed signal and said second delayed signal, wherein said delay control circuitry controls which of said first and second delayed signals is output by said multiplexer.

7. The circuit of claim 1 further comprising:

core circuitry, wherein said clock signal is supplied to said core circuitry for use in synchronization of said core circuitry'"'"'s operation.

8. The circuit of claim 7 wherein said operating voltage is supplied to said core circuitry.

9. The circuit of claim 1 further comprising:

track control circuitry that inputs a track signal to each of said at least one delay element to control whether an amount of delay in a delayed signal output by the respective delay element varies based on the observed value of said operating voltage.

10. The circuit of claim 1 further comprising:

a plurality of delay elements; and

track control circuitry that inputs a track signal to each of said plurality of delay elements to control whether an amount of delay in a delayed signal output by the respective delay element varies based on the observed value of said operating voltage.

11. The circuit of claim 10 wherein if said track signal input to one of said plurality of delay elements is a first value, that delay element varies the amount of delay in a delay signal that it outputs based on the observed value of said operating voltage, and if said track signal input to that delay element is a different value than said first value, that delay element maintains a constant delay in a delay signal that it outputs.

12. The circuit of claim 11 wherein if said track signal input to said one of said plurality of delay elements is said first value, that delay element increases the amount of delay in the delay signal that it outputs responsive to a decrease in the observed value of said operating voltage and that delay element decreases the amount of delay in the delay signal that it outputs responsive to an increase in the observed value of said operating voltage.

13. The circuit of claim 1 wherein said at least one delay element receives said operating voltage and a fixed voltage, and said at least one delay element receives a track signal;

and wherein said at least one delay element comprises a pass gate that is supplied the fixed voltage if the track signal is a first value, thereby maintaining a constant amount of delay in a delayed signal output by the at least one delay element, and said pass gate is supplied the operating voltage if the track signal is a second value, thereby varying the amount of delay in the delayed signal output by the at least one delay element.

14. The circuit of claim 1 wherein said circuit is an integrated circuit.

15. Voltage-to-frequency conversion circuitry comprising:

at least one delay element that receives a clock signal and outputs a delayed clock signal having an amount of delay relative to the received clock signal, said at least one delay element including a transfer gate to which either a fixed voltage supply or a variable voltage supply is provided based on the value of a track signal, wherein if the variable voltage supply is provided to said transfer gate, the transfer gate varies the amount of said delay of the delayed clock signal responsive to changes in the variable voltage supply.

16. The voltage-to-frequency conversion circuitry of claim 15 further comprising:

comparator circuitry for comparing the clock signal with the delayed clock signal.

17. The voltage-to-frequency conversion circuitry of claim 16 further comprising:

clock control circuitry operable to dynamically control the frequency of the clock signal based at least in part on the comparison of the received clock signal with the delayed clock signal.

18. The voltage-to-frequency conversion circuitry of claim 15 further comprising:

a plurality of delay elements each operable to impart a delay to the received clock signal for generating the delayed clock signal.

19. The voltage-to-frequency conversion circuitry of claim 18 further comprising:

delay control circuitry for selecting a desired number of the plurality of delay elements to be used in imparting a delay to the received clock signal for generating the delayed clock signal.

20. The voltage-to-frequency conversion circuitry of claim 18 further comprising:

track control circuitry for inputting a track signal to each of the plurality of delay elements to control whether said transfer gate of each delay element varies the amount of delay imparted by the delay element to the received clock signal responsive to changes in the variable voltage supply.

21. The voltage-to-frequency conversion circuitry of claim 15 implemented on an integrated circuit, wherein said integrated circuit is supplied said variable voltage and said fixed voltage.

22. A method comprising:

receiving a first phase of a chip'"'"'s clock signal into a delay line circuit of the chip;

generating with at least one delay element of the delay line circuit a delayed clock signal having a phase that is delayed relative to the first phase of the received clock signal;

comparing with comparison circuitry on the chip the generated delayed clock signal with a later phase of the chip'"'"'s clock signal, the later phase of the chip'"'"'s clock signal being later than the first phase of the chip'"'"'s clock signal; and

determining with clock control circuitry on the chip whether to change the frequency of the chip'"'"'s clock signal, based at least in part on the comparison of the generated delayed clock signal with the later phase of the chip'"'"'s clock signal.

23. The method of claim 22 wherein a plurality of delay elements are included in the delay line circuit, the method further comprising:

outputting with delay control circuitry on the chip a delay control signal for controlling which ones of the plurality of delay elements are to be used for imparting a delay to the received clock signal for generating the delayed clock signal.

24. The method of claim 22 wherein a plurality of delay elements are included in the delay line circuit, the method further comprising:

outputting with track control circuitry on the chip a track signal for controlling which ones of the plurality of delay elements are to dynamically change their respective delay that they impart to the received clock signal responsive to observed changes in a variable operating voltage of the chip.

25. The method of claim 24 wherein:

if the track signal has a first value, the amount of delay generated by a delay element receiving such track signal varies across a range of different operating voltages observed for the chip; and

if the track signal has a second value, the amount of delay generated by the delay element receiving such track signal remains constant across said range of different operating voltages observed for the chip.

26. The method of claim 22 further comprising:

programming the at least one delay element regarding whether an amount of delay that the at least one delay element imparts to the received clock signal is sensitive to changes in a variable operating voltage of the chip.

27. The method of claim 22 further comprising:

generating with said at least delay element said delayed clock signal having said phase that is delayed relative to the first phase of the received clock signal by an amount that varies responsive to an observed operating voltage of the chip.

28. A method comprising:

observing with on-chip circuitry an operating voltage of a chip; and

receiving a clock signal and generating a delayed clock signal having a delayed amount relative to the received clock signal with on-chip circuitry, wherein said delayed amount is programmatically selectable to vary responsive to changes in the observed operating voltage.

29. The method of claim 28 wherein the on-chip circuitry includes at least one delay element that is used for imparting a delay to the received clock signal for generating the delayed clock signal, and wherein the on-chip circuitry includes track control circuitry that outputs a track signal for controlling whether a delay amount imparted by each of the at least one delay element varies responsive to the changes in the observed operating voltage.

30. The method of claim 28 further comprising:

supplying said operating voltage to the chip;

supplying a fixed voltage to the chip; and

selectively controlling whether a transfer gate included in the on-chip circuitry is provided the operating voltage or the fixed voltage, wherein if the transfer gate is provided the operating voltage the delayed amount of the delayed clock signal generated by the on-chip circuitry varies across a range of values observed for the operating voltage, and wherein if the transfer gate is provided the fixed voltage the delayed amount of the delayed clock signal generated by the on-chip circuitry remains constant across the range of values observed for the operating voltage.

31. A method comprising:

fabricating a chip that includes clock management circuitry for dynamically managing a clock signal of the chip responsive to observed changes in a variable operating voltage of the chip; and

programming the clock management circuitry on the fabricated chip to tailor its sensitivity to said observed changes in the chip'"'"'s variable operating voltage.

32. The method of claim 31 wherein said clock management circuitry comprises at least one delay element, said at least one delay element receiving the chip'"'"'s clock signal and imparting an amount of delay to the received clock signal for generating a delayed clock signal.

33. The method of claim 32 further comprising:

comparing the generated delayed clock signal with the chip'"'"'s clock signal; and

based at least in part on the comparison, determining whether to change the chip'"'"'s clock signal'"'"'s frequency.

34. The method of claim 32 wherein said programming comprises:

selectively controlling whether a transfer gate included in the at least one delay element is provided the variable operating voltage or a fixed voltage, wherein if the transfer gate is provided the variable operating voltage the delayed amount of the delayed clock signal generated by the at least one delay element varies across a range of values observed for the operating voltage, and wherein if the transfer gate is provided the fixed voltage the delayed amount of the delayed clock signal generated by the at least one delay element remains constant across the range of values observed for the operating voltage.