Apparatus for providing a jittered clock signal and apparatus for providing a random bit

• US 20050231294A1
• Filed: 09/03/2004
• Published: 10/20/2005
• Est. Priority Date: 09/04/2003
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Luzzi, Raimondo
• Granted Patent: US 7,193,481 B2
• Time in Patent Office: Days
• US Class Current: 331/78
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

An apparatus for providing a jittered clock signal has a reverse-biased diode. The reversed-biased diode has a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current. The apparatus for providing a jittered clock signal further has a unit for periodically increasing the reverse voltage of the diode to a value, which is above a switching value and the apparatus has a unit for comparing the reverse voltage of the diode to the switching value and for outputting a jittered clock signal dependent on the comparison.

Claims

1. An apparatus for providing a jittered clock signal, comprising:

a reverse-biased diode, wherein the diode comprises a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current;

a unit for periodically increasing the reverse voltage of the diode to a voltage which is above a switching value; and

a unit for comparing the reverse voltage of the diode to the switching value and for outputting a jittered clock signal dependant on the comparison.

2. The apparatus for providing a jittered clock signal according to claim 1, wherein the unit for periodically increasing the reverse voltage provides an input clock signal to the diode, wherein the input clock signal comprises an active state and a tri-state state, wherein the active state provides a supply voltage with a supply voltage value being above the switching value, and wherein the active state is periodically interrupted by the tri-state state for a discharge time period in which the reverse voltage of the diode decreases from the supply voltage value to below the switching value.

3. The apparatus for providing a jittered clock signal according to claim 1, wherein the unit for periodically increasing the reverse voltage is connected to the outputted clock signal and the period in which the reverse voltage is increased depends on the outputted clock signal.

4. The apparatus for providing a jittered clock signal according to claim 1, wherein the unit for periodically increasing the reverse voltage of the diode is a tri-state buffer.

5. The apparatus for providing a jittered clock signal according to claim 1, wherein the reverse-biased diode is a reversed-biased P-N junction.

6. The apparatus for providing a jittered clock signal according to claim 1, wherein the unit for comparing the reverse voltage to the switching value and for outputting a jittered clock signal is an inverter that is connected to the diode.

7. An apparatus for providing a random bit comprising:

a first apparatus for providing a first jittered clock signal and a second apparatus for providing a second jittered clock signal, both comprising a reverse-biased diode, wherein the diode comprises a leakage current which decreases a reverse voltage on the diode, time-dependent on a shot-noise of the leakage current, a unit for periodically increasing the reverse voltage of the diode to a voltage which is above a switching value, and a first unit for comparing the reverse voltage of the diode to the switching value and for outputting a first and a second jittered clock signal, respectively, dependant on the comparison; and

a second unit for comparing the first and the second jittered clock signal and for outputting a random bit dependent an a result of the comparison.

8. The apparatus for providing a random bit according to claim 7, comprising a unit for aligning a mean switching time of the first jittered clock signal to a mean switching time of the second jittered clock signal and for providing a first and a second delayed jittered clock signal to the second unit for comparing.

9. The apparatus for providing a random bit according to claim 7, wherein the second unit for comparing and for outputting is a D-flip-flop.

10. The apparatus for providing a random bit according to claim 7, wherein the second unit for comparing further comprises an XOR gate, and wherein an additional random bit is provided dependent on a time delay between edges of the first and the second jittered clock signal.