Patent application cmos imager for cellular applications and methods of using such

• US 20050231620A1
• Filed: 05/29/2002
• Published: 10/20/2005
• Est. Priority Date: 05/29/2001
• Status: Active Grant

• Current Assignee: Transchip Israel Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Transchip Israel Limited (Samsung Electronics Co. Ltd.)
• Inventors: Antsiferov, Ilia, Voronov, German, Galambos, Tiberiu C., Elmakias, Yair, Shnayder, Alexander, Furman, Ben, Fraenkel, Miriam
• Granted Patent: US 7,420,602 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 11/20 Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 17/002 for television cameras
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/71 Circuitry for evaluating the brightness variation
• CPC Class Codes: H04N 23/73 by influencing the exposure time
• CPC Class Codes: H04N 23/745 Detection of flicker frequency or suppression of flicker wherein the flicker is caused by illumination, e.g. due to fluorescent tube illumination or pulsed LED illumination
• CPC Class Codes: H04N 23/83 specially adapted for colour signals
• CPC Class Codes: H04N 23/88 for colour balance, e.g. white-balance circuits or colour temperature control
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/633 by using optical black pixels
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 5/16 Circuitry for reinsertion of dc and slowly varying components of signal; Circuitry for preservation of black or white level
• CPC Class Codes: H04N 9/69 for modifying the colour signals by gamma correction controlling camera response for colour signals H04N23/83
• CPC Class Codes: H04N 9/73 Colour balance circuits, e.g. white balance circuits or colour temperature control camera processing pipelines for colour balance H04N23/88

Abstract

Systems, methods and devices related to detecting and transmitting images. Imaging systems and devices, as well as methods of using such that are provided herein include flicker detection and/or correction; and/or built-in self test associated with various analog circuitry in the imaging devices; and/or power reduction ability; and/or pixels with charge evacuation functionality; and/or a parallel to serial conversion unit and associated serial output interface; and/or other advanced functionality.

Claims

1. A CMOS imaging device, the CMOS imaging device comprising:

a pixel array;

a selector, wherein the selector is operable to select between an input derived from the pixel array and at least one reference input, and wherein the selection between the input derived from the pixel array and the at least one reference input is at least in part based on a signal derived from a digital domain; and

an analog to digital converter, wherein the analog to digital converter is operable to convert a signal derived from the selector to the digital domain.

2. The CMOS imaging device of claim 1, wherein the signal derived from the selector is an output of the selector that is passed through an analog processing circuit.

3. The CMOS imaging device of claim 2, wherein the analog processing circuit consists of one or more circuits selected from a group consisting of:

a level shift circuit, a programmable offset circuit, and a programmable gain amplifier.

4. The CMOS imaging device of claim 2, the CMOS imaging device further comprising:

an analog processing selector, wherein the analog processing selector is operable to bypass one or more portions of the analog processing circuit.

5. The CMOS imaging device of claim 1, the CMOS imaging device further comprising:

a comparator receiving an output from the analog to digital converter, wherein the comparator is selected from a group consisting of;

a programmable hardware comparator, a programmable software comparator, and a hardwired comparator.

6. The CMOS imaging device of claim 1, wherein the pixel array includes at least one pseudo-pixel, the CMOS imaging device further comprising:

a pixel array selector, wherein the pixel array selector is operable to select the at least one pseudo-pixel, and wherein the input derived from the pixel array is derived from the pseudo-pixel.

7. The CMOS imaging device of claim 6, the CMOS imaging device further comprising:

a column amplifier, wherein the column amplifier receives an output from the pseudo-pixel, and amplifies the output from the pseudo-pixel; and

wherein the input derived from the pixel array is derived via the column amplifier.

8. The CMOS imaging device of claim 1, wherein the reference input to the selector is a pixel under reset, the CMOS imaging device further comprising:

a circuit for selecting the pixel under reset; and

wherein the selector is operable to provide a differential pair consisting of the input derived from the pixel array and the pixel under reset.

9. The CMOS imaging device of claim 1, wherein at least one of the reference inputs to the selector is tied to a pad of the CMOS imaging device.

10. The CMOS imaging device of claim 1, wherein at least one of the reference inputs to the selector comprises one or more voltages generated internal to the CMOS imaging device.

11. The CMOS imaging device of claim 1, wherein the input derived from the pixel array and the at least one reference input are both differential inputs.

12. A method for testing analog functionality of a CMOS imaging device in the digital domain, the method comprising:

providing a pixel array;

providing a selector, wherein the selector is operable to select between an input derived from the pixel array and at least one reference input;

providing an analog to digital converter, wherein the analog to digital converter is operable to convert a signal derived from the selector to the digital domain;

asserting a selection signal in the digital domain, wherein a derivative of the selection signal is input to the selector and at least in part controls the selection between the input derived from the pixel array and the reference input; and

analyzing an output of the analog to digital converter to verify that the CMOS imaging device is functional.

13. The method of claim 12, wherein the reference input is a differential input, and wherein the reference input is a combination of two signals selected from a group consisting of:

a common voltage, a negative reference voltage, and a positive reference voltage.

14. The method of claim 13, wherein asserting the selection signal causes the reference input to be selected, the method further comprising:

providing an analog processing circuit, wherein the analog processing circuit receives the reference input from the selector, and processes the reference input, and wherein the signal derived from the selector is the processed reference input.

15. The method of claim 14, wherein the analog processing circuit comprises a first circuit and a second circuit, the method further comprising:

bypassing the first circuit.

16. The method of claim 12, wherein the analyzing the output of the analog to digital converter comprises comparing the output of the analog to digital converter to determine if the output is within a predefined range.

17. The method of claim 12, wherein the pixel array includes at least one pseudo-pixel, the method further comprising:

selecting the pseudo-pixel, wherein an output of the pseudo pixel is not sensitive to an illumination of the CMOS imaging device, and wherein the input derived from the pixel array is derived from the output of the pseudo-pixel; and

wherein asserting the selection signal causes the input from the pixel array to be selected.

18. The method of claim 17, the method further comprising:

providing a column amplifier, wherein the input derived from the pixel array is derived via the column amplifier.

19. The method of claim 12, wherein the reference input is a differential input, and wherein at least one differential signal of the reference input is generated external to the CMOS imaging device.

20. The method of claim 12, wherein the input derived from the pixel array is a differential input, wherein the at least one reference input comprises a reset level, and wherein the selection between the input derived from the pixel array and the reference input includes selecting one of the differential signals associated with the input derived from the pixel array and the reset level, and providing the input derived from the pixel array and the reset level as a differential pair.

21. The method of claim 20, the method further comprising:

resetting at least one pixel in the pixel array; and

selecting the at least one reset pixel, wherein the input derived from the pixel array is derived from the at least one reset pixel.

22. A CMOS imager, wherein the CMOS imager comprises:

an image sensor, wherein the image sensor includes one or more rows of pixels, and wherein each of the pixels provides a pixel value;

a storage element;

a summing circuit, wherein the summing circuit is operable to sum the pixel values for each of the one or more rows to create row sums, and to store the row sums to the storage element; and

a programmable core, wherein the programmable core includes instructions executable by the programmable core to;

determine a first energy value and a second energy value associated with the row sums;

compare the first energy value and the second energy value to estimate a flicker frequency; and

constrain an exposure duration associated with the image sensor to approximate a multiple of the flicker duration.

23. The CMOS imager of claim 22, wherein the summing circuit is further operable to calculate row sums for a plurality of frames, wherein each of the plurality of frames includes pixel values from the two or more rows of pixels, and wherein the instructions are further executable by the programmable core to:

determine a first energy value and a second energy value associated with the row sums for each frame;

calculate a variance between first energy values across the plurality of frames;

calculate a variance between second energy values across the plurality of frames; and

wherein the comparing the first energy value and the second energy value to estimate a flicker frequency comprises comparing the variance of the first energy values with the variance of the second energy values.

24. The CMOS imager of claim 23, wherein the instructions are further executable by the programmable core to:

compare the variance of the first energy values with the variance of the second energy values, wherein the larger is a greater variance; and

comparing the greater variance with a predefined threshold, wherein the constraining the exposure frequency is done when the greater variance is greater than the predefined threshold.

25. The CMOS imager of claim 24, wherein the CMOS imager further comprises:

a confidence counter, wherein the confidence counter is incremented whenever the estimated flicker frequency is approximately a first frequency, and decremented whenever the estimated flicker frequency is not approximately the first frequency.

26. The CMOS imager of claim 25, wherein the constraining the exposure frequency is done when the confidence counter changes its sign.

27. The CMOS imager of claim 22, wherein the CMOS imager further comprises:

an interrupt associated with the summing circuit, wherein assertion of the interrupt indicates that summing for the one or more rows of pixels is complete.

28. The CMOS imager of claim 27, wherein the instructions are further executable by the programmable core to receive the interrupt.

29. The CMOS imager of claim 22, wherein the summing circuit is further operable to calculate row sums for a plurality of frames, wherein each of the plurality of frames includes pixel values from the two or more rows of pixels, and wherein the CMOS imager further comprises:

an interrupt associated with the summing circuit, wherein assertion of the interrupt indicates that summing for the two or more rows of pixels for a frame is complete; and

wherein the instructions are further executable by the programmable core to;

receive the interrupt;

determine a first energy value and a second energy value associated with the row sums for each frame;

determine if a sufficient number of frames have been received to

calculate a variance between first energy values and a variance between second energy values;

calculate the variance between first energy values across the plurality of frames;

calculate the variance between second energy values across the plurality of frames; and

wherein the comparing the first energy value and the second energy value to estimate a flicker frequency comprises comparing the variance of the first energy values with the variance of the second energy values.

30. The CMOS imager of claim 22, wherein determining the first energy value and the second energy value comprises calculating an exact Fourier component for the first energy value and for the second energy value.

31. A method for automatically detecting flicker in an imaging device, the method comprising:

providing an imaging device, wherein the imaging device includes an image sensor with two or more rows of pixels, and wherein each of the pixels provides a pixel value;

retrieving at least a portion of the two or more rows of pixels, and summing the pixel values to create a row sum for each of the rows of pixels;

determining a first energy value and a second energy value associated with the row sums; and

comparing the first energy value and the second energy value to estimate a flicker frequency.

32. The method of claim 31, the method farther comprising:

constraining an exposure duration associated with the image sensor to approximate a multiple of the flicker frequency period.

33. The method of claim 31, wherein determining the first energy value and the second energy value comprises calculating an approximate Fourier component for the first energy value and for the second energy value.

34. The method of claim 31, wherein the retrieving at least a portion of each of the two or more rows of pixels, sunning the pixel values, and determining a first energy value and a second energy value is performed for each of a plurality of frames, the method further comprising:

calculating a variance between first energy values across the plurality of frames;

calculating a variance between second energy values across the plurality of frames; and

wherein the comparing the first energy value and the second energy value to estimate a flicker frequency comprises comparing the variance of the first energy values with the variance of the second energy values.

35. The method of claim 34, the method further comprising:

comparing the variance of the first energy values with the variance of the second energy values, wherein the larger is a greater variance; and

comparing the greater variance with a predefined threshold, wherein the constraining the exposure duration is done when the greater variance is greater than the predefined threshold.

36. The method of claim 35, the method further comprising:

incrementing a confidence count whenever the estimated flicker frequency is approximately a first frequency, and

decrementing the confidence count whenever the estimated flicker frequency is not approximately the first frequency.

37. The method of claim 36, wherein the constraining the exposure duration is done when the confidence counter changes sign.

38. The method of claim 31, wherein the summing the pixel values to create a row sum for each of the rows of pixels is done by a summing circuit included in the imaging device, the method further comprising:

issuing an interrupt associated with the summing circuit, wherein the interrupt indicates that summing for the two or more rows of pixels is complete.

39. The method of claim 38, the method further comprising:

receiving the interrupt, wherein determining the first and the second energy values is at least in part triggered by the interrupt.

40. An imaging device, wherein the imaging device comprises:

a pixel array, wherein the pixel array comprises a plurality of rows, wherein each of the plurality of rows comprises a plurality of pixels, and wherein each of the plurality of pixels provides a pixel value;

a summing circuit, wherein the summing circuit is operable to sum the pixel values for one or more of the plurality of rows to create row sums;

an interrupt associated with the summing circuit, wherein the interrupt indicates that summing is complete for one or more of the plurality of rows; and

a programmable core, wherein the programmable core includes instructions executable by the programmable core to;

receive the interrupt;

determine a first energy value and a second energy value associated with the row sums for each frame of a plurality of frames;

calculate a variance between first energy values across the plurality of frames;

calculate a variance between second energy values across the plurality of frames; and

compare the variance of the first energy values with the variance of the second energy values, wherein the larger is a greater variance.

41. The imaging device of claim 40, wherein the instructions are further executable by the programmable core to:

constrain the exposure duration to a multiple of the flicker frequency period.

42. A CMOS imager, wherein the CMOS imager comprises:

an image sensor;

a sub-sample control system, wherein the sub-sample control system is operable to identify one or more signals from the image sensor that are not processed;

an analog processing circuit, wherein the analog processing circuit receives the one or more signals from the image sensor at one or more inputs; and

a processing control system, wherein the processing control system is operable to limit switching of the one or more inputs.

43. The CMOS imager of claim 42, wherein the analog processing circuit comprises a column amplifier, and wherein the one or more inputs are inputs to the column amplifier.

44. The CMOS imager of claim 42, wherein the analog processing circuit comprises a level shift circuit, and wherein the one or more inputs are inputs to the level shift circuit.

45. The CMOS imager of claim 42, wherein the analog processing circuit comprises a programmable offset circuit, and wherein the one or more inputs are inputs to the programmable offset circuit.

46. The CMOS imager of claim 42, wherein the processing control system is operable to maintain a common mode feedback loop of an amplifier associated with the analog processing circuit in an active state, while limiting switching of the one or more inputs.

47. The CMOS imager of claim 42, the CMOS imager further comprising:

a digital processing circuit, wherein the processing control system is further operable to disable the digital processing circuit.

48. A method for processing images in a power sensitive application, the method comprising:

providing a CMOS imager, wherein the CMOS imager includes a pixel array, and an analog processing circuit;

defining a first portion and a second portion of the pixel array, wherein the first portion of the pixel array includes a output image area and the second portion of the pixel array includes a dropped image area;

receiving a pixel signal from the second portion of the pixel array; and

placing the analog processing circuit in a standby mode, wherein the pixel signal from the second portion of the pixel array is not processed.

49. The method of claim 48, wherein placing the analog processing circuit in the standby mode comprises:

limiting switching of one or more inputs to the analog processing circuit.

50. The method of claim 48, wherein placing the analog processing circuit in the standby mode comprises:

electrically coupling one or more inputs of the analog processing circuit to a static voltage, wherein switching of the analog processing circuit is reduced.

51. The method of claim 48, wherein placing the analog processing circuit in the standby mode comprises:

electrically coupling one or more inputs of the analog processing circuit to a static voltage, while maintaining switching associated with a common mode feedback loop of one or more amplifiers associated with the analog processing circuit, wherein switching of the analog processing circuit is reduced, and bias currents are reduced while maintaining the one or more amplifiers at its inertial state.

52. The method of claim 48, the method further comprising:

receiving a pixel signal from the first portion of the pixel array; and

placing the analog processing circuit in an operational mode, wherein the pixel signal from the first portion of the pixel array is processed.

53. The method of claim 48, wherein the power sensitive application comprises video transmission via a cellular telephone.

54. The method of claim 48, wherein the power sensitive application comprises image detection and processing using a mobile device.

55. The method of claim 54, wherein the mobile device is selected from a group consisting of a cellular telephone, a personal digital assistant, and a laptop computer.

56. The method of claim 48, wherein the CMOS imager further comprises a digital processing circuit, the method further comprising:

disabling the digital processing circuit, wherein the pixel signal from the second portion of the pixel array is not processed.

57. The method of claim 56, wherein disabling the digital processing circuit comprises:

gating at least one clock driving the digital processing circuit.

58. The method of claim 52, wherein the CMOS imager further comprises a digital processing circuit, the method further comprising:

enabling the digital processing circuit, wherein the pixel signal from the first portion of the pixel array is processed.

59. The method of claim 48, wherein the analog processing circuit comprises:

a column amplifier; and

a level shift circuit.

60. The method of claim 59, wherein the analog processing circuit further comprises:

a black level offset;

a programmable gain amplifier; and

an ADC.

61. The method of claim 56, wherein the digital processing circuit includes a translation unit.

62. A method for reducing power consumption in an imaging device, the method comprising:

providing an imaging device including an image sensor and an analog processing circuit;

sub-sampling the image sensor, wherein a first portion of the image sensor is not processed;

receiving an image signal from the first portion of the image sensor; and

placing the analog processing circuit in a standby state, wherein the image signal from the first portion is not processed.

63. The method of claim 62, wherein placing the analog processing circuit in a standby state comprises:

limiting switching of one or more inputs to the analog processing circuit.

64. The method of claim 62, wherein the analog processing circuit comprises:

a level shift circuit;

a programmable offset circuit; and

a programmable gain amplifier.

65. The method of claim 64, wherein placing the analog processing circuit in a standby state comprises:

electrically coupling one or more inputs of the analog processing circuit to a static voltage, wherein switching of the analog processing circuit is reduced.

66. The method of claim 65, wherein placing the analog processing circuit in a standby state further comprises:

maintaining switching associated with a common mode feedback loop of one or more amplifiers associated with the analog processing circuit, wherein the one or more amplifiers are maintained in an inertial state, and a bias current associated with the amplifiers is reduced.

67. The method of claim 62, wherein sub-sampling the image sensor is done to create a bandwidth matched image output from the imaging device.

68. The method of claim 62, the method further comprising:

receiving an image signal from a second portion of the image sensor, wherein the second portion the image sensor is processed; and

placing the analog processing circuit in an operational mode, wherein the image signal from the second portion is processed.

69. The method of claim 68, wherein placing the analog processing circuit in an operational mode comprises electrically coupling one or more inputs of the analog processing circuit to the image signal from the second portion.

70. The method of claim 62, wherein the imaging device further comprises a digital processing circuit, the method further comprising:

disabling the digital processing circuit.

71. A CMOS imager, wherein the CMOS imager comprises

an image sensor;

a parallel to serial data conversion unit, wherein the parallel to serial data conversion unit receives an image derived from the image sensor and converts the image to a serial data stream; and

a serial output interface, wherein the serial output interface provides access to the serial data stream.

72. The CMOS imager of claim 71, wherein the image sensor comprises one or more pixels, and wherein the one or more pixels include a charge evacuation element.

73. The CMOS imager of claim 71, wherein the serial output interface includes a clock signal and a data signal, and wherein the clock signal is only active when valid data is presented on the data signal.

74. The CMOS imager of claim 71, wherein the serial output includes a clock signal, a data signal, and a qualifying signal, and wherein the qualifying signal indicates the presence of valid data on the data signal.