Circuit for electrostatic discharge protection

• US 20050231878A1
• Filed: 03/22/2002
• Published: 10/20/2005
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Krasin, Alexander
• Granted Patent: US 7,154,719 B2
• Time in Patent Office: Days
• US Class Current: 361/111
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

A circuit providing protection against electrostatic discharge (ESD) for internal elements of an Integrated Circuit (IC) is connected to a power rail (VDD) and a ground rail (VSS) and to an inverter (INV) of a clamp preamplifier. The protection circuit comprises a PMOSFET resistor (R) with a gate connected to said ground rail (VSS), a drain connected to said inverter'"'"'s (INV) input node (ESD_RC), a source and a bulk connected to said power rail (VDD). The circuit also comprises an NMOSFET capacitor (C1) with a gate connected to said inverter'"'"'s (INV) input node (ESD_RC), a drain, a source and a bulk connected to said ground rail (VSS), and a PMOSFET connector (C2) with a gate connected to said inverter'"'"'s (INV) input node (ESD_RC), a drain, a source connected to said ground rail (VSS) and a bulk connected to said power rail (VDD).

Claims

1. A circuit providing protection against electrostatic discharge (ESD) for internal elements of an Integrated Circuit (IC), the circuit being connected to a power rail and a ground rail and to an inverter of a clamp preamplifier, said circuit comprises:

a PMOSFET resistor with a gate connected to said ground rail, a drain connected to said inverter'"'"'s input node, a source and a bulk connected to said power rail,

an NMOSFET capacitor with a gate connected to said inverter'"'"'s input node, a drain, a source and a bulk connected to said ground rail, and

a PMOSFET capacitor with a gate connected to said inverter'"'"'s input node, a, drain, a source connected to said ground rail and a bulk connected to said power rail.

2. The circuit according to claim 1 wherein said NMOSFET capacitor has a non-linear characteristic.

3. The circuit according to claim 1 wherein said PMOSFET capacitor has a non-linear characteristic.

4. The circuit according to claim 1 wherein said NMOSFET capacitor and said PMOSFET capacitor have non-linear characteristics.

5. The circuit according to any of the claim 1 wherein ratio of capacitance of said PMOSFET capacitor to capacitance of said NMOSFET capacitor decreases when voltage at said power rail exceeds NMOSFET threshold.

6. An integrated circuit comprising a circuit providing protection against an electrostatic discharge event according to any of claim 1.