Sequential program-verify method with result buffering

• US 20050232019A1
• Filed: 03/29/2005
• Published: 10/20/2005
• Est. Priority Date: 03/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Villani, Paolo, Vorraro, Giovanni Francesco
• Granted Patent: US 7,184,310 B2
• Time in Patent Office: Days
• US Class Current: 365/185.220
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A sequential program-verify method is used in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments. The method includes the steps of: writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common alignment, verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value, buffering the fault values, and in response to the verification of all the blocks of cells providing an indication of the alignments being defective according to tpe fault values.

Claims

1. A sequential program-verify method for use in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments, the method comprising:

writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common one of the alignments;

verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value;

buffering the fault values; and

in response to the verification of all the blocks of cells, providing an indication of the alignments being defective according to the fault values.

2. The method according to claim 1 wherein the step of writing includes programming all the blocks of cells.

3. The method according to claim 1 wherein the memory device further includes a plurality of read/write units each one having a first latch and a second latch, and means for selectively coupling each read/write unit with the cells belonging to a corresponding one of the alignments, and wherein:

the step of verifying including reading the block of cells into the corresponding second latches, and

the step of buffering including latching the fault values into the corresponding first latches.

4. The method according to claim 3 wherein the step of latching the fault values includes:

setting each first latch according to the value latched in the corresponding second latch.

5. The method according to claim 4, further including the step of:

resetting each first latch to a condition corresponding to the deassertion of the fault value before verifying the blocks of cells, wherein;

the step of setting each first latch according to the value latched in the corresponding second latch including coupling the first latch with the second latch to leave the first latch unaffected when the value latched in the second latch is indicative of successfully programming of the corresponding cell or to switch the first latch to a further condition corresponding to the assertion of the fault value otherwise.

6. The method according to claim 3, wherein the second latch is a cache latch for inputting a value to be written into the corresponding cell, and wherein the first latch is a main latch for receiving the value latched in the second latch and programming the corresponding cell accordingly.

7. The method according to claim 1 wherein the memory device includes a flash memory with NAND architecture.

8. A logic controller readable medium including a program code for a logic controller in a non-volatile memory device including a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments, wherein, when the program code is run on the controller, the program code causes the controller to perform a method comprising:

writing a set of target values into a plurality of blocks of cells, the corresponding cells of each block belonging to a common one of the alignments;

verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in the cell of the block belonging to the alignment with the corresponding target value;

buffering the fault values; and

in response to the verification of all the blocks of cells, providing an indication of the alignments being defective according to the fault values.

9. The logic controller readable medium according to claim 8 wherein the memory device further includes a plurality of read/write units each one having a first latch and a second latch, and means for selectively coupling each read/write unit with the cells belonging to a corresponding one of the alignments, and wherein:

verifying includes reading the block of cells into the corresponding second latches, and

buffering includes latching the fault values into the corresponding first latches.

10. The logic controller readable medium according to claim 9 wherein latching the fault values includes:

setting each first latch according to the value latched in the corresponding second latch.

11. The logic controller readable medium according to claim 10, wherein the program code also causes the controller to:

reset each first latch to a condition corresponding to the deassertion of the fault value before verifying the blocks of cells, wherein;

setting each first latch according to the value latched in the corresponding second latch includes coupling the first latch with the second latch to leave the first latch unaffected when the value latched in the second latch is indicative of the successfully programming of the corresponding cell or to switch the first latch to a further condition corresponding to the assertion of the fault value otherwise.

12. The logic controller readable medium according to claim 9, wherein the second latch is a cache latch for inputting a value to be written into the corresponding cell, and wherein the first latch is a main latch for receiving the value latched in the second latch and programming the corresponding cell accordingly.

13. A non-volatile memory device, comprising:

a plurality of memory cells each one for storing a logic value, the cells being arranged into a plurality of alignments;

means for writing a set of target values into a plurality of blocks of the cells, the corresponding cells of each block belonging to a common one of the alignments;

means for verifying each block of cells in succession to assert a fault value for each alignment in response to a non-compliance of the value stored in one of the cells of the block belonging to the alignment with the corresponding target value;

means for buffering the fault values; and

means responsive to the verification of all the blocks of cells for providing an indication of the alignments being defective according to the fault values.

14. The memory device according to claim 13 wherein the means for buffering include a first latch that latches the fault values and the means for verifying include a second latch that receives logic values read from each block of cells.

15. The memory device according to claim 14 wherein the means for buffering include means for setting the first latch according to the value latched in the second latch.

16. The memory device according to claim 14, further including:

means for resetting each first latch to a condition corresponding to the deassertion of the fault value before verifying the blocks of cells, wherein;

the means for setting each first latch include means for coupling the first latch with the second latch to leave the first latch unaffected when the value latched in the second latch is indicative of successfully programming of the corresponding cell or to switch the first latch to a further condition corresponding to the assertion of the fault value otherwise.

17. The memory device according to claim 14, wherein the second latch is a cache latch for inputting a value to be written into the corresponding cell, and wherein the first latch is a main latch for receiving the value latched in the second latch and programming the corresponding cell accordingly.

18. The memory device according to claim 13 wherein the plurality of memory cells is of a flash memory with NAND architecture.