Semiconductor memory device having redundancy cell array shared by a plurality of memory cell arrays

• US 20050232035A1
• Filed: 06/30/2004
• Published: 10/20/2005
• Est. Priority Date: 04/16/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takashima, Daisaburo, Miyakawa, Tadashi
• Granted Patent: US 7,209,398 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/22 using ferroelectric elements

Abstract

A semiconductor memory device includes memory cell arrays, a redundancy cell array shared by the memory cell arrays, a correction capacitance, and switching circuits arranged in correspondence with the memory cell arrays. Each memory cell array includes ferroelectric cells arranged at the intersections between word lines and bit lines. The redundancy cell array includes spare ferroelectric cells arranged at the intersections between spare word lines and redundancy bit lines. The number of spare ferroelectric cells connected to the redundancy bit line is smaller than that of ferroelectric cells connected to the bit line in each memory cell array. The correction capacitance is connected to the redundancy bit line to make its capacitance equivalent to that of the bit line. When a replaced ferroelectric cell in the memory cell array is selected, the switching circuits select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

Claims

1. A semiconductor memory device comprising:

a main cell array which includes a plurality of memory cell arrays, the memory cell arrays having ferroelectric cells arranged at intersections between word lines and bit lines;

a redundancy cell array which is arranged independently of the main cell array and shared by said plurality of memory cell arrays, the redundancy cell array having spare ferroelectric cells arranged at intersections between spare word lines and redundancy bit lines, the spare ferroelectric cells connected to the redundancy bit line being smaller in number than the ferroelectric cells connected to the bit line in memory cell arrays in the main cell array;

a correction capacitance which is connected to the redundancy bit line to make a capacitance of the redundancy bit line equivalent to that of the bit line; and

switching circuits which are arranged in correspondence with the memory cell arrays and configured to, when a replaced ferroelectric cell in the main cell array is selected, select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

2. A device according to claim 1, wherein

the ferroelectric cells in the memory cell arrays comprises a plurality of first unit cells connected in series, and a first block select transistor which connects the first unit cells to the bit line in response to a first block select signal,

the ferroelectric cells in the redundancy cell array comprises a plurality of second unit cells connected in series, and a second block select transistor which connects the second unit cells to the redundancy bit line in response to a second block select signal, and

the first unit cells and the second unit cells has a cell transistor and a ferroelectric capacitor whose two terminals are connected between a source and a drain of the cell transistor.

3. A device according to claim 1, wherein the correction capacitance includes at least one of a ferroelectric capacitor, a linear capacitor, and a parasitic capacitance, in which one electrode is connected to the redundancy bit line, and the other electrode is connected to a ground potential.

4. A device according to claim 1, wherein the switching circuits selects, on the basis of fuse data which stores an address of a defective cell, one of data read out from a corresponding memory cell array through a main read/write data line and data read out from the redundancy cell array through a spare read/write data line.

5. A device according to claim 1, which further comprises an address buffer circuit to which an address signal is input,

a redundancy fuse circuit which receives an output signal from the address buffer circuit, the redundancy fuse circuit storing an address of a defective cell in the main cell array,

a row decoder/PL control circuit which receives the output signal from the address buffer circuit and an output signal from a control circuit and selectively drives the word lines and a plate line in the main cell array, and

an RD row decoder/RDPL control circuit which receives the output signal from the redundancy fuse circuit and an output signal from the row decoder/PL control circuit and selectively drives the spare word lines and a spare plate line in the redundancy cell array, and

in which when the address of the defective cell, which is stored in the redundancy fuse circuit, is selected, the switching circuits select the spare ferroelectric cells.

6. A device according to claim 5, further comprising input/output buffers which are arranged in correspondence with the switching circuits and connected to the switching circuits through read/write data lines,

wherein the control circuit controls the address buffer circuit, the row decoder/PL control circuit, and the input/output buffers.

7. A device according to claim 6, wherein the switching circuits comprises a first transfer gate which is arranged between a main read/write data line and the read/write data line and controlled on the basis of a signal representing that a defective address output from the redundancy fuse circuit is accessed, and a second transfer gate which is arranged between a spare read/write data line and the read/write data line and controlled on the basis of an inverted signal of the signal representing that the defective address output from the redundancy fuse circuit is accessed.

8. A semiconductor memory device comprising:

a main cell array which includes a plurality of memory cell arrays, the memory cell arrays having ferroelectric cells arranged at intersections between word lines and bit lines;

a redundancy cell array which is arranged independently of the main cell array and shared by said plurality of memory cell arrays, the redundancy cell array having spare ferroelectric cells arranged at intersections between spare word lines and redundancy bit lines, the spare ferroelectric cells connected to the redundancy bit line being smaller in number than the ferroelectric cells connected to the bit line in memory cell arrays in the main cell array, and the redundancy cell array including a plurality of redundancy bit lines which are connected in series to make a capacitance of the bit line equivalent to that of the redundancy bit line; and

switching circuits which are arranged in correspondence with the memory cell arrays and configured to, when a replaced ferroelectric cell in the main cell array is selected, select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell.

9. A device according to claim 8, wherein

the ferroelectric cells in the memory cell arrays comprises a plurality of first unit cells connected in series, and a first block select transistor which connects the first unit cells to the bit line in response to a first block select signal,

the ferroelectric cells in the redundancy cell array comprises a plurality of second unit cells connected in series, and a second block select transistor which connects the second unit cells to the redundancy bit line in response to a second block select signal, and

the first unit cells and the second unit cells has a cell transistor and a ferroelectric capacitor whose two terminals are connected between a source and a drain of the cell transistor.

10. A device according to claim 8, wherein the switching circuits selects, on the basis of fuse data which stores an address of a defective cell, one of data read out from a corresponding memory cell array through a main read/write data line and data read out from the redundancy cell array through a spare read/write data line.

11. A device according to claim 8, which further comprises an address buffer circuit to which an address signal is input,

a redundancy fuse circuit which receives an output signal from the address buffer circuit, the redundancy fuse circuit storing an address of a defective cell in the main cell array,

a row decoder/PL control circuit which receives the output signal from the address buffer circuit and an output signal from a control circuit and selectively drives the word lines and a plate line in the main cell array,

an RD row decoder/RDPL control circuit which receives the output signal from the redundancy fuse circuit and an output signal from the row decoder/PL control circuit and selectively drives the spare word lines and a spare plate line in the redundancy cell array, and

an I/O selection circuit which is configured to receive the output signal from the redundancy fuse circuit and an output signal from the RD row decoder/RDPL control circuit and control an operation of the switching circuits, and

in which the switching circuits execute a selection operation on the basis of an output signal from the I/O selection circuit.

12. A device according to claim 11, further comprising input/output buffers which are arranged in correspondence with the switching circuits and connected to the switching circuits through read/write data lines,

wherein the control circuit controls the address buffer circuit, the row decoder/PL control circuit, and the input/output buffers.

13. A device according to claim 12, wherein the switching circuits comprise a plurality of switch circuits which are controlled for bits on the basis of a signal representing that a defective address output from the I/O selection circuit is accessed, the switch circuit comprising a first transfer gate which is arranged between a main read/write data line and the read/write data line and controlled for bits on the basis of the signal representing that the defective address output from the I/O selection circuit is accessed, and a second transfer gate which is arranged between a spare read/write data line and the read/write data line and controlled on the basis of an inverted signal of the signal representing that the defective address output from the I/O selection circuit is accessed.

14. A device according to claim 8, wherein said plurality of redundancy bit lines are connected in series in a zigzag manner.

15. A semiconductor memory device comprising:

a main cell array which includes a plurality of memory cell arrays, the memory cell arrays having ferroelectric cells arranged at intersections between word lines and bit lines, the ferroelectric cells comprising i first unit cells connected in series, and a first block select transistor which selects the first unit cells, and the first unit cells having a cell transistor and a ferroelectric capacitor whose two terminals are connected between a source and a drain of the cell transistor;

a redundancy cell array which is arranged independently of the main cell array and shared by said plurality of memory cell arrays, the redundancy cell array having spare ferroelectric cells arranged at intersections between spare word lines and redundancy bit lines, the spare ferroelectric cells comprising j (j<

i) second unit cells connected in series, and a second block select transistor which selects the second unit cells, and the second unit cells having a cell transistor and a ferroelectric capacitor whose two terminals are connected between a source and a drain of the cell transistor; and

switching circuits which are arranged in correspondence with the memory cell arrays and configured to, when a replaced ferroelectric cell in the main cell array is selected, select a corresponding spare ferroelectric cell in place of the replaced ferroelectric cell,

wherein the first block select transistors connected to bit lines in memory cell arrays in the main cell array are equal in number to the second block select transistors connected to redundancy bit lines in the redundancy cell array.

16. A device according to claim 15, wherein the switching circuits selects, on the basis of fuse data which stores an address of a defective cell, one of data read out from a corresponding memory cell array through a main read/write data line and data read out from the redundancy cell array through a spare read/write data line.

17. A device according to claim 15, which further comprises an address buffer circuit to which an address signal is input,

a redundancy fuse circuit which receives an output signal from the address buffer circuit, the redundancy fuse circuit storing an address of a defective cell in the main cell array,

a row decoder/PL control circuit which receives the output signal from the address buffer circuit and an output signal from the control circuit and selectively drives the word lines and a plate line in the main cell array, and

an RD row decoder/RDPL control circuit which receives the output signal from the redundancy fuse circuit and an output signal from the row decoder/PL control circuit and selectively drives the spare word lines and a spare plate line in the redundancy cell array, and

in which when the address of the defective cell, which is stored in the redundancy fuse circuit, is selected, the switching circuits select the spare ferroelectric cells.

18. A device according to claim 17, further comprising input/output buffers which are arranged in correspondence with the switching circuits and connected to the switching circuits through read/write data lines, and

a control circuit which controls the address buffer circuit, the row decoder/PL control circuit, and the input/output buffers.

19. A device according to claim 18, wherein the switching circuits comprises a first transfer gate which is arranged between a main read/write data line and the read/write data line and controlled on the basis of a signal representing that a defective address output from the redundancy fuse circuit is accessed, and a second transfer gate which is arranged between a spare read/write data line and the read/write data line and controlled on the basis of an inverted signal of the signal representing that the defective address output from the redundancy fuse circuit is accessed.