System bridge and timeclock for RF controlled lighting systems
First Claim
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1. A bridge, comprising:
- a display device for presenting information to a user;
a memory for storing information;
a transmitter for transmitting messages to a first and second subnet on a predetermined RF;
a receiver for receiving messages from the first and second subnet on the predetermined RF;
an Input/Output device for receiving or sending information; and
a processor, wherein said processor is operatively connected to said memory, transmitter, receiver, display device and Input/Output device, and wherein said processor transmits a link claim to the first and second subnets, a first command and random wait time to the first subnet, and a maximum random wait time to the second subnet by way of said transmitter, and receives an acknowledgement from the first subnet by way of said receiver.
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Abstract
A method for operatively interconnecting a first and second lighting control subnet is disclosed. In the method, a link claim is transmitted to the first and second lighting control subnets from a bridge. The link claim directs the first and second lighting control subnets to wait for a lighting control command, which is transmitted to the lighting control command to the first lighting control subnet. A random wait time is assigned to the first lighting control subnet and a maximum random wait time is assigned to the second lighting control subnets. Finally, an acknowledgement is received from the first lighting control subnet.
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Citations
12 Claims
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1. A bridge, comprising:
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a display device for presenting information to a user;
a memory for storing information;
a transmitter for transmitting messages to a first and second subnet on a predetermined RF;
a receiver for receiving messages from the first and second subnet on the predetermined RF;
an Input/Output device for receiving or sending information; and
a processor, wherein said processor is operatively connected to said memory, transmitter, receiver, display device and Input/Output device, and wherein said processor transmits a link claim to the first and second subnets, a first command and random wait time to the first subnet, and a maximum random wait time to the second subnet by way of said transmitter, and receives an acknowledgement from the first subnet by way of said receiver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification