Synchronous data transfer system for time-sensitive data in packet-switched networks

• US 20050232307A1
• Filed: 07/10/2002
• Published: 10/20/2005
• Est. Priority Date: 07/10/2002
• Status: Active Grant

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Andersson, Leif Arne Jorgen, Fullemann, John
• Granted Patent: US 7,200,768 B2
• Time in Patent Office: Days
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0658 Clock or time synchronisation among packet nodes
• CPC Class Codes: H04J 3/0682 by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
• CPC Class Codes: H04L 12/44 Star or tree networks

Abstract

A transmission arrangement and method permits time-sensitive data to be transmitted through a packet-switched network and arrive synchronously at separate end points without synchronising all payload carrying nodes in the network. This is achieved by propagating a timing reference through the network from the sending node to the end nodes, each end node adjusting that phase of its local frequency generator to this timing reference. The sending node then sends data structure information to the end nodes, enabling the end nodes to regenerate the timing and structure of the synchronous data stream. Finally delay information is sent to each end node that allows the end nodes to adjust the start of synchronous data transmission by an amount such that all will commence transmission substantially simultaneously. With this information the end nodes independently recreate a signal in synchronisation. This solution has the advantage that the network infrastructure can remain substantially unchanged, although the timing sensitive application can treat the network as if it were a synchronised network.

Claims

1-21. -21. (canceled)

22. A data transmission link for transmitting time-sensitive data, comprising:

a first node connected to a plurality of end nodes by a broadband packet-switched network, wherein each end node is connected to at least one end terminal, each of said end nodes including;

timing generation circuitry adapted to generate an output timing signal that is phase locked to a received reference timing signal originating at said first node;

means for receiving data structure information from said first node and identifying a data structure format from said information for transmitting time-sensitive data between said end nodes and said end terminals;

a delay signal generator for generating a delay signal in response to delay information received from said first node; and

,

data conversion means communicating with said delay signal generating means, said data structure receiving means and said timing generation circuitry, said data conversion means adapted to receive payload data from said first node and retransmit payload data identified as time-sensitive data in a synchronous manner to said end terminal, wherein the timing of said payload data transmission is adjusted in each end node on the basis of said received timing signal, said received data structure format and said received delay signal, such that all end nodes transmit said payload data substantially simultaneously.

23. The link as recited in claim 22, wherein at least one intermediate node is arranged between said first node and at least one of said end nodes, each said intermediate node including timing generation circuitry adapted to generate an output timing signal that is phase locked to a received reference timing signal originating at said first node, and to propagate said output timing signal to said end node.

24. The link as recited in claim 22, wherein said means for receiving data structure information from said first node further includes:

means for extracting a data transmission start time marker from said information, said data transmission start marker indicating an absolute start to transmit time for transmitting time-sensitive data between said end nodes and said end terminals.

25. The link as recited in claim 24, wherein said delay signal generator is arranged to adjust the timing of said transmission start time marker by said generated delay.

26. The link as recited in claim 22, wherein each said end node is operative to determine a node transmission delay between said end node and said first node and to communicate this node transmission delay to said first node, and wherein said first node is operative to determine the maximum node transmission delay from each end node and communicate this maximum node transmission delay to all end nodes as delay information.

27. The link as recited in claim 26, wherein said node transmission delay is the round-trip delay between and end node and said first node.

28. The link as recited in claim 22, wherein said timing generation circuitry includes:

means for extracting a timing reference from a received signal;

means for phase locking a generated timing signal to said timing reference; and

,

means for imposing said phase locked timing signal on an output signal to generate said output timing signal.

29. The link as recited in claim 22, wherein said network is an Ethernet.

30. A method for transmitting time-sensitive data through a packet-switched network between a first node and a plurality of end nodes, wherein each end node is connected to at least one end terminal, said method comprising the steps of:

propagating a timing signal through said network from said first node to each said end nodes;

transmitting a signal indicative of a data structure type from the first node to each end node, said data structure type identifying the data format for transmission from said end node to said end terminals;

transmitting a delay figure from said first node to each end node, said delay figure being indicative of the maximum transmission delay between said first node and any one of said end nodes; and

,

transmitting payload data between said first node and said end terminals, whereby the payload data transmitted between each end node and the corresponding end terminal is formatted in said identified data structure format in accordance with said timing signal and adjusted in dependence on said delay figure such that payload data transmission from each end node to each end terminal occurs substantially synchronously.

31. The method as recited in claim 30, further including the step of generating said delay figure by determining a maximum transmission delay between any end node and said first node.

32. The method as recited in claim 31, further including the steps of:

sending a delay message from an end node to said first node;

returning the delay message to the end node;

calculating a transmission delay based on the return time of said message; and

,

communicating this transmission delay to said first node.

33. The method as recited in claim 30, wherein said step of transmitting a signal indicative of a data structure type includes the step of transmitting a burst of information messages, wherein the interval between each information message is indicative of the transmission repetition rate of the identified data structure from said end node to said terminals.

34. The method as recited in claim 33, further including the steps of:

in each end node, determining the interval between each information message;

generating a periodic timing marker corresponding to said interval; and

,

utilising said timing marker to commence transmission of an identified data structure of payload data to said end terminal.

35. The method as recited in claim 34, further including the step of:

in each end node, adjusting said periodic timing marker in dependence on said delay figure.

36. A node for use in a broadband packet-switched network adapted to receive packet switched-data in a first format from a sending node in said network and transmit synchronous data to an end terminal located outside said network in a second format, said node comprising:

timing generation circuitry adapted to generate an output signal timing signal that is phase locked to a received reference timing signal;

means for receiving data structure information indicative of the data structure and repetition rate of said second format;

a delay signal generator for generating a delay signal in response to delay information received from said first node; and

,

data conversion means communicating with said delay signal generating means, said data structure receiving means and said timing generation circuitry, said data conversion means being adapted to receive payload data in said first data format and retransmit payload data identified as time-sensitive data in said second format, wherein the timing of said payload data transmission is adjusted on the basis of said received timing signal, said received data structure format and said received delay signal.

37. The node as recited in claim 36, further including means for identifying start of data received in said first format, wherein said start of data represents the start of a unit of payload data to be transmitted in said second format.

38. The node as recited in claim 36, wherein said means for receiving data structure information from said first node further includes means for extracting a data transmission start time marker from said information, said data transmission start marker indicating an absolute start to transmit time for transmitting time-sensitive data between said end nodes and said end terminals.

39. The node as recited in claim 38, wherein said delay signal generator is arranged to adjust the timing of said transmission start time marker by said generated delay.

40. The node as recited in claim 36, wherein said node is further adapted to determine a node transmission delay from said sending node.

41. The node as recited in claim 40, wherein said node transmission delay is the round-trip delay between said node and said sending node.

42. The node as recited in claim 36, wherein said timing generation circuitry includes means for extracting a timing reference from a received signal, means for phase locking a generated timing signal to said timing reference and means for imposing said phase locked timing signal on an output signal to generate said output timing signal.