CMOS image sensor

• US 20050233493A1
• Filed: 06/01/2005
• Published: 10/20/2005
• Est. Priority Date: 12/09/2002
• Status: Active Grant

• Current Assignee: Quantum Semiconductor LLC
• Original Assignee: Quantum Semiconductor LLC
• Inventors: Augusto, Carlos J.R.P.
• Granted Patent: US 7,153,720 B2
• Time in Patent Office: Days
• US Class Current: 438/51
• CPC Class Codes: G02B 1/005 made of photonic crystals or photonic band gap materials photonic band-gap structures or photonic lattices in integrated optics G02B6/1225; photonic band-gap structures or photonic lattices in optical fibres G02B6/02295
• CPC Class Codes: G02B 5/008 Surface plasmon devices diffractive gratings with a pitch less than or comparable to the wavelength G02B5/1809; surface plasmons in integrated optics G02B6/1226; optical analysis of materials by means of surface plasmons G01N21/553
• CPC Class Codes: G02B 5/201 in the form of arrays
• CPC Class Codes: G02B 5/208 for use with infrared or ultraviolet radiation, e.g. for separating visible light from infrared and/or ultraviolet radiation
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14625 Optical elements or arrangements associated with the device
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/02165 using interference filters, e.g. multilayer dielectric filters interference filters G02B5/28
• CPC Class Codes: H01L 31/105 the potential barrier being of the PIN type

Abstract

Light sensing devices are monolithically integrates with CMOS devices on Thin-Film Silicon-On-insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI) substrates. Photodiode active layers are epitaxially grown on the front-side of the substrate and after full processing of the front-side of the substrate, the substrate material is removed under the buried insulator (buried oxide). Monolithically integrated structures are then fabricated on the back of the buried oxide. The back-side is then bonded to a new substrate that is transparent to the wavelengths of interest. For example, quartz, sapphire, glass, or plastic, are suitable for the visible range. Back-side illumination of the sensor matrix is thereby allowed, with light traveling through the structures fabricated on the back of the substrate, opposite to the side on which CMOS is made.

Claims

1. Process architecture to fabricate CMOS image sensors allowing back-side illumination, comprising the steps of:

(a) Selection of a Thin-Film Silicon-On-Insulator (TF-SOI) or Thin-Film Germanium-On-Insulator (TF-GeOI) substrate,

(b) Epitaxial growth of photo-diode active layers on the front-side of the substrate,

(c) Fabrication of dense metal interconnects over the sensor matrix, on the front-side of the substrate,

(d) Removal of substrate under the buried insulator (buried oxide) after full processing of the front-side of the TF-SOI or TF-GeOI substrates,

(e) Fabrication of monolithically integrated structures on the back of the buried oxide,

(f) Bonding of the back-side to a new mechanical substrate that is transparent to the wavelengths of interest.

2. Process architecture according to claim 1, in which the back-side structure comprises at least one conventional color filter, embedded between the buried oxide and the transparent mechanical substrate.

3. Process architecture according to claim 1, in which in-pixel homojunction or heterojunction epitaxial capacitors are made directly on the epitaxially grown photo-diode layers.

5. Process architecture according to claim 1, in which in-pixel MOS capacitors are made directly on the epitaxially grown photo-diode layers.

6. Process architecture according to claim 1, in which the in-pixel MIM capacitors are made over the area of the pixel, during the fabrication of interconnects.

7. Process architecture according to claim 1, in which the back-side structure is a monolithically integrated Surface Plasmon Polariton (SPP) structure.

8. Process architecture according to claim 7, in which the Surface Plasmon Polariton (SPP) device, arranged into 1D or 2D arrays comprises:

Thin-film of conducting material formed over a film of an insulating material with a high dielectric constant, which was formed over a film of another insulating material with a low dielectric constant;

The low dielectric constant material has holes across the entire thickness of the film, that are filled with the high dielectric constant material. In those regions the high dielectric material has a T-shaped cross-section;

The holes in the low dielectric constant material are aligned with the light-sensors to which the electromagnetic radiation will be coupled;

The metal film deposited over the high dielectric constant material is patterned into an array of isolated pixels of regular shapes, such as a square, a rectangle or a hexagon, that can be replicated to completely fill a surface;

The holes in the low dielectric constant material are much smaller than the area of the isolated metal films—

pixels;

The array of isolated metal films—

pixels—

is positioned at the image plane of a lens, while the bottom of the holes filled with the high dielectric constant material are positioned as closely as possible to the absorption region of a photo-sensor;

Resonant surface plasmon polaritons are excited by electromagnetic radiation impinging on the top surface of the isolated metal films, and propagate to the bottom of the holes, where the electromagnetic radiation is coupled to, and absorbed by, a photo-sensor;

The top surface of the metal film is covered with different insulator materials having different dielectric constants as a method to tune the wavelength of operation;

The 1D or 2D matrices of metal film structures are fabricated on the buried oxide of back-side illuminated TF-SOI or TF-GeOI substrates, with high precision alignment to the devices fabricated on the front-side of the substrates, in particular to the photo-diodes.

9. Process architecture according to claim 8, in which the surface of the metal film, where light is gathered, and the surface of the holes, where light is leaked out, is much smaller than the wavelength of light, without the occurrence of diffraction.

10. Process architecture according to claim 8 or 9, in which the metal film is perforated with slits and/or holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and/or polarization selectivity.

11. Process architecture according to claim 7, in which the Surface Plasmon Polariton (SPP) device, arranged into 1D or 2D arrays comprises:

Conductor film having at least one slit or hole centrally positioned and surrounded by symmetrically arranged corrugations on front and back surfaces of the film;

the top view of the pixels has a regular shape, such as a square, a rectangle or a hexagon, that can be replicated to completely fill a surface;

The bottom and top surfaces of the metal film can be interfaced with insulating materials having significantly different dielectric constants;

The top surface of the film is positioned at the image plane of a lens, while the light beam exiting the bottom surface has sub-wavelength cross-section, and very low divergence;

In each isolated conductor film, the hole or slit from which at the bottom surface the light beam exits with very low divergence, is aligned with high precision to the photo-diodes inside the sensor pixels.

12. Process architecture according to claim 11, in which the surface of the metal film, where light is gathered, and the surface of the holes, where light is leaked out, is much smaller than the wavelength of light, without the occurrence of diffraction.

13. Process architecture according to claim 11 or 12, in which the metal film is perforated with slits and/or holes of desirable shapes, size and pitch in order to enhance wavelength selectivity and/or polarization selectivity.

14. Process architecture according to claim 11, in which the Surface Plasmon Polariton (SPP) device, in which the 1D or 2D arrays are fabricated on the buried oxide of back-side illuminated TF-SOI or TF-GeOI substrates, with high precision alignment to the devices fabricated on the front-side of the substrates, in particular to the photo-diodes.

15. Process architecture according to claim 11, in which the 1D or 2D arrays are fabricated on top of a dielectric layer formed on the last metal layer of the complete metal stack providing interconnects on the front-side of the wafer, suitable for front-side illumination, regardless of substrate type.

16. Process architecture according to claim 1, in which the back-side structure comprises a monolithically integrated “

Perfect Lens”

or “

Superlens”

structure.

17. CMOS image sensors made in accordance with the process architecture of any of the preceding claims.