Method for fabricating semiconductor device

• US 20050233573A1
• Filed: 06/29/2004
• Published: 10/20/2005
• Est. Priority Date: 04/19/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Kang Tae
• Granted Patent: US 7,056,841 B2
• Time in Patent Office: Days
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating a semiconductor device for reducing coupling noise resulting from high integration of devices, comprises the steps of forming a plurality of metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate having a predetermined under layer; forming an insulating interlayer on an entire surface of the semiconductor substrate so that the metal wiring leads are covered with the insulating interlayer; and ion-implanting conductive impurities having a plurality opposite to each other into side end layers of the insulating interlayer disposed between the metal wiring leads so as to reduce the internal charges electrified due to an applied external electric field.

Claims

1. A method of fabricating a semiconductor device so as to reduce coupling noise between metal wiring leads, the method comprising the steps of:

i) forming a plurality of metal leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate;

ii) forming an insulating interlayer on the entire surface of the semiconductor substrate so as to cover the metal wiring leads with the insulating interlayer; and

iii) ion-implanting conductive impurities having a polarity opposite to each other, one into either side end layers of the insulating interlayer between the metal wiring leads so as to reduce the internal charges in the dielectric that are electrified due to an applied external electric field.

2. The method as claimed in claim 1, wherein, in step iii), conductive impurities are implanted having a polarity opposite to the polarity of the internal charges electrified due to the external electric field.

3. The method as claimed in claim 1, wherein, in step iii), the coupling noise between the metal wiring leads is controlled by adjusting any one parameter selected from the group consisting of position, energy, and dose of ion implantation.

4. A method for fabricating a semiconductor device for reducing coupling noise between metal wiring leads, the method comprising the steps of:

i) forming a plurality of lower metal wiring leads spaced from each other by a predetermined distance and arranged on a semiconductor substrate;

ii) forming a first insulating interlayer on an entire surface of the semiconductor substrate so that the lower metal wiring leads are covered with the first insulating interlayer; and

iii) forming a plurality of upper metal wiring leads spaced from each other by a predetermined distance and arranged on the first insulating interlayer; and

iv) forming a second insulating interlayer on the first insulating interlayer so that the upper metal wiring leads are covered with the second insulating interlayer, wherein conductive impurities having a polarity opposite to each other are ion-implanted into both side end layers of the first insulating interlayer between the lower metal wiring leads, in both side end layers of the first insulating interlayer and in the second insulating interlayer between the lower metal wiring leads and the upper metal wirings, and in both side end layers of the second insulating interlayer between the upper metal wiring leads.

5. The method as claimed in claim 4, wherein, the ion implantation is achieved by implanting conductive impurities having a polarity opposite to the polarity of the internal charges generated by the applied external electric field.

6. The method as claimed in claim 4, wherein, the coupling noise between the metal wiring leads is controlled by adjusting at least one parameter of the ion implantation, the parameters being selected from the group consisting of position, energy, and dose of the ion implantation.