High data rate transmitter and receiver

• US 20050233710A1
• Filed: 02/09/2005
• Published: 10/20/2005
• Est. Priority Date: 12/06/2001
• Status: Active Grant

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Holding 73 LLC (Intellectual Ventures LLC)
• Inventors: Lakkis, Ismail, Santhoff, John, Bahreini, Yasaman
• Granted Patent: US 8,045,935 B2
• Time in Patent Office: Days
• US Class Current: 455/102
• CPC Class Codes: H04B 1/71632 Signal aspects H04B1/7172 and H04B1/7176 take precedence
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence

Abstract

A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Claims

1. A transmitter comprising:

a baseband processor, structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval;

a local oscillator generating a clock signal at a second timing interval; and

a digital circuit configured to combine the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency.

2. The transmitter of claim 1, further comprising a data interface structured to pass the data to the baseband processor, the data interface selected from a group consisting of:

Universal Serial Bus standard, an IEEE 1394 standard, a Peripheral Component Interconnect standard, a Peripheral Component Interconnect Express standard, a MILSPEC-1760 standard, an Ethernet standard, and a MILSPEC-1553 standard.

3. The transmitter of claim 1, wherein the digital circuit includes an adjustable chipping code to spread the transmission signal.

4. The transmitter of claim 3, wherein the chipping code is selected from a group consisting of:

a 256-bit code, a 64-bit code, a 32-bit code, a 16-bit code, an 8-bit code, a 4-bit code, a 2-bit code, and a 1-bit code.

5. The transmitter of claim 3, wherein the adjustable chipping code is adjusted in response to a communication channel condition, the communication channel condition selected from:

a bit-error-rate, a received signal strength indicator, and a packet error rate.

6. The transmitter of claim 1, wherein the baseband processor is structured to determine a data encoding rate, the data encoding rate selected from a group consisting of:

full rate encoding, ⅛

^th rate encoding, ¼

rate encoding, ⅜

^th rate encoding ½

rate encoding, ⅝

^th rate encoding, ⅞

^th rate encoding, and ¾

rate encoding.

7. The transmitter of claim 1, wherein the first timing interval can range from approximately 133 picoseconds to approximately 2 nanoseconds.

8. The transmitter of claim 1, wherein the second timing interval can range from approximately 100 picoseconds to approximately 333 picoseconds.

9. The transmitter of claim 1, wherein the second timing interval is an integer multiple of the first timing interval.

10. The transmitter of claim 1, wherein a ratio of the second timing interval to the first timing interval can range from about 20 percent to about 200 percent.

11. The transmitter of claim 1, wherein the digital circuit is selected from a group consisting of:

an “

exclusive or”

gate, an “

and”

gate, and a multiplexer.

12. The transmitter of claim 1, wherein the transmission frequency can range from about 3.0 Giga-Hertz to about 11.0 Giga-Hertz.

13. The transmitter of claim 1, wherein the transmission signal is transmitted through a wire media to a receiver, the wire media selected from a group consisting of:

a an optical fiber ribbon, a fiber optic cable, a single mode fiber optic cable, a multi-mode fiber optic cable, a twisted pair wire, an unshielded twisted pair wire, a plenum wire, a PVC wire, and a coaxial cable.

15. The method of claim 1, further comprising the step of adjusting a chipping code to spread the transmission signal.

14. A method of transmitting data, the method comprising the steps of:

providing data;

converting the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval;

generating a clock signal at a second timing interval; and

combining the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency.

16. The method of claim 14, wherein the chipping code is selected from a group consisting of:

a 256-bit code, a 64-bit code, a 32-bit code, a 16-bit code, an 8-bit code, a 4-bit code, a 2-bit code, and a 1-bit code.

17. The method of claim 14, wherein the step of adjusting the chipping code is performed in response to a communication channel condition, the communication channel condition selected from:

a bit-error-rate, a received signal strength indicator, and a packet error rate.

18. The method of claim 14, further comprising determining a data encoding rate, the data encoding rate selected from a group consisting of:

full rate encoding, ½

rate encoding, and ¾

rate encoding.

19. The method of claim 14, wherein the first timing interval can range from approximately 133 picoseconds to approximately 2 nanoseconds.

20. The method of claim 14, wherein the second timing interval can range from approximately 100 picoseconds to approximately 333 picoseconds.

21. The method of claim 14, wherein the second timing interval is an integer multiple of the first timing interval.

22. The method of claim 14, wherein a ratio of the second timing interval to the first timing interval can range from about 20 percent to about 200 percent.

23. The method of claim 14, wherein the transmission frequency can range from about 3.0 Giga-Hertz to about 11.0 Giga-Hertz.

24. A transmitter comprising:

a data interface;

a medium access controller configured to receive data from the data interface and arrange the data into a plurality of frames;

a baseband processor configured to receive the plurality of frames and configured to produce a multiplicity of high and low signal values representing the data, with each high and low signal value having a first timing interval;

a local oscillator generating a clock signal at a second timing interval; and

a digital circuit configured to combine the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency.

25. The transmitter of claim 24, wherein the baseband processor segments the data from the plurality of frames into a plurality of data packets.

26. The transmitter of claim 25, wherein the baseband processors adds a synchronization code to each of the plurality of data packets.

27. The transmitter of claim 25, wherein the baseband processor adds a single physical layer header to the plurality of data packets.

28. The transmitter of claim 27, wherein the physical layer header comprises a plurality of synchronization code blocks.

29. The transmitter of claim 24, further comprising a forward error correction encoder that encodes the data with a forward error correction algorithm.

30. The transmitter of claim 29, wherein the forward error correction encoder is a low density parity check algorithm.

31. A receiver comprising:

a front end configured to receive a communication signal that has a fractional bandwidth in a range between approximately 20 percent and approximately 200 percent; and

an analog to digital converter configured to directly convert the radio frequency signal into a data signal.

32. The receiver of claim 31, further comprising a baseband processor configured to receive the data signal and to produce a plurality of data frames;

and

a medium access controller configured to receive the plurality of data frames and convert the data frames to data.

33. The receiver of claim 31, where the communication signal is an ultra-wideband signal.

34. The receiver of claim 31, where the center frequency of the communication signal can range from approximately 3.0 Giga-Hertz to approximately 11.0 Giga-Hertz.

35. The receiver of claim 31, where the digital to analog converter is selected from a group consisting of:

a 1-bit converter, a 2-bit converter, a 4-bit converter, a 6-bit converter, and an 8-bit converter.

36. The receiver of claim 32, wherein the digital baseband processor includes a poly-phase filter.

37. The receiver of claim 32, wherein the digital baseband processor decimates of the data signal.

38. The receiver of claim 32, wherein the digital baseband processor de-spreads the data signal by determining a de-spreading code, where the de-spreading code is selected from a group consisting of:

a 1-bit code, a 2-bit code, a 4-bit code, an 8-bit code, a 16-bit code, a 32-bit code, a 64-bit code, a 128-bit code, and a 256-bit code.

39. The receiver of claim 32, wherein the digital baseband processor calculates a channel impulse response.

40. The receiver of claim 32, wherein the digital baseband processor descrambles the data signal.

41. The receiver of claim 32, wherein the baseband processor de-interleaves the data signal.

42. The receiver of claim 32, wherein the baseband processor includes a forward error detection decoding algorithm.

43. The receiver of claim 42, wherein the forward error detection decoding algorithm is a low density parity check algorithm.

44. The receiver of claim 32, wherein the data frames comprise a physical layer header, a medium access control header, a rate field and a plurality of data packets.

45. The receiver of claim 44, wherein the physical layer header, the medium access control header, and the plurality of data packets have different spreading codes.

46. The receiver of claim 31, wherein the communication signal is transmitted through a wire media from a transmitter, the wire media selected from a group consisting of:

a an optical fiber ribbon, a fiber optic cable, a single mode fiber optic cable, a multi-e mode fiber optic cable, a twisted pair wire, an unshielded twisted pair wire, a plenum wire, a PVC wire, and a coaxial cable.

47. The receiver of claim 31, wherein the front end comprises at least two receive antennas.

48. The receiver of claim 47, wherein the at least two receive antennas are separated by a distance of greater than one wavelength of a center frequency of the communication signal.