Multi-protocol serial interface system

• US 20050235088A1
• Filed: 03/24/2005
• Published: 10/20/2005
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Hee Bok
• Granted Patent: US 7,555,589 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system.

Claims

1. A multi-protocol serial interface system comprising:

a multi-protocol port pin array comprising a plurality of port pins which interface with an external system for exchanging data with the external system;

a transport protocol change FPGA for determining roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data;

a pull-up change FPGA for regulating pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA; and

a memory for storing data processed in the transport protocol change FPGA unit and exchanged with the external system.

2. The multi-protocol serial interface system according to claim 1, further comprising a CPU for processing data stored in the memory depending on a predetermined process.

3. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA includes a plurality of coding cells for storing the code data.

4. The multi-protocol serial interface system according to claim 3, wherein the coding cell is a resistor for storing data using a nonvolatile capacitor.

5. The multi-protocol serial interface system according to claim 1, wherein the transport protocol change FPGA is programmed so that two input/output terminals for a power voltage and a ground voltage are fixed as a specific terminal regardless of the change of the protocol.

6. The multi-protocol serial interface system according to claim 1, wherein the pull-up change FPGA comprises:

a plurality of coding cells for storing pull-up load regulating data to regulate pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA; and

a load unit for regulating pull-up load of the corresponding port pin in response to the pull-up load regulating data.

7. The multi-protocol serial interface system according to claim 6, wherein the coding cell is a resistor for storing data using a nonvolatile capacitor.

8. The multi-protocol serial interface system according to claim 6, wherein the load unit is a MOS transistor for applying the power voltage to the corresponding port pin in response to the pull-up load regulating data.