Memory controller, semiconductor integrated circuit device, semiconductor device, microcomputer, and electronic device

• US 20050235101A1
• Filed: 04/06/2005
• Published: 10/20/2005
• Est. Priority Date: 04/20/2004
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Sakurai, Mikio
• Granted Patent: US 7,366,828 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G06F 13/1636 using refresh

Abstract

A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control for the second memory; and an arbiter that adjusts the timing of outputting a signal generated for the first memory and another signal generated for the second memory to a bus, wherein, with a judgment that the signal from the first memory controller is an auto-refresh request, a refresh request signal for the first memory is outputted even while the second memory is being accessed.

Claims

1. A memory controller connectable with a first memory which requires refresh, and a second memory which shares part of a bus with the first memory and does not require refresh, comprising:

a first memory controller that conducts access control and auto-refresh control for the first memory;

a second memory controller that conducts access control for the second memory; and

an arbiter that adjusts a timing of outputting a signal that is generated for the first memory by the first memory controller and another signal that is generated for the second memory by the second memory controller to a bus that is connected to at least one of the first memory and the second memory,

wherein the arbiter judges whether a signal from the first memory controller is an auto-refresh request signal and, if the signal is an auto-refresh request, controls a timing of outputting a refresh request signal for the first memory even while the second memory is being accessed.

2. The memory controller according to claim 1, wherein a bus that outputs a signal required for refresh control for the first memory is not shared with the second memory.

3. The memory controller according to claim 1, wherein a bus that outputs a chip select signal, a row address strobe (RAS) signal, a column address strobe (CAS) signal, and a write enable (WE) signal, which are used for auto-refresh control in the case where the first memory is a synchronous DRAM, is not shared with the second memory.

4. The memory controller according to claim 1, wherein the first memory and the second memory share a data bus and an address bus.

5. A semiconductor integrated circuit device comprising the memory controller according to claim 1.

6. A semiconductor device comprising the memory controller according to claim 1, a first memory, and a second memory.

7. A microcomputer comprising the memory controller according to claim 1.

8. An electronic device comprising:

the microcomputer according to claim 7;

means for inputting data to be processed by the microcomputer; and

LCD outputting means for outputting data processed by the microcomputer.