Multiple-capture DFT system for scan-based integrated circuits

• US 20050235186A1
• Filed: 06/14/2005
• Published: 10/20/2005
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Wang, Hsin-Po, Wang, Laung-Terng, Wen, Xiaoqing, Hsu, Chi-Chan, Kao, Shih-Chia, Hsu, Fei-Sheng, Lin, Meng-Chyi
• Granted Patent: US 7,451,371 B2
• Time in Patent Office: Days
• US Class Current: 714/728
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318552 Clock circuits details
• CPC Class Codes: G01R 31/31858 Delay testing
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit'"'"'s fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

Claims

1-100. -100. (canceled)

101. A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly during scan-test, where N>

1, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode;

said method comprising the steps of;

(a) generating and loading N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly, by applying first selected shift clock pulses to all said scan cells in said scan mode for loading or shifting-in said N predetermined stimuli to all said scan cells, during a shift operation;

(b) applying an ordered sequence of clock pulses to all said scan cells within said N clock domains during a capture operation, the ordered sequence of clock pulses comprising at least a second selected shift clock pulse and a capture clock pulse from two or more selected capture clocks, for controlling two or more clock domains, in a sequential order, wherein one said selected capture clock must contain at least one said second selected shift clock pulse and the other said selected capture clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected capture clock controlling the clock domain selectively contains at least two consecutive capture clock pulses or a second selected shift clock pulse followed by at least one capture clock pulse to launch the transition and capture the output response; and

(c) comparing N output responses directly with their expected output responses for all said scan cells within said N clock domains and indicating errors immediately, by applying said first selected shift clock pulses to all said scan cells in said scan mode for comparing or shifting-out said N output responses for comparison with said expected output responses, during a compare operation.

102. The method of claim 101, wherein each said capture clock is programmable to contain said ordered sequence of clock pulses, for performing said capture operation on all said scan cells within a selected clock domain controlled by said capture clock.

103. The method of claim 101, further comprising providing two or more scan enable (SE) signals each for controlling a selected clock domain;

wherein all said scan enable (SE) signals are used to switch said shift/compare and capture operation; and

wherein each said scan enable (SE) signal is selectively generated internally or controlled externally, and can be selectively operated at said selected clock domain?s rated clock speed or at a selected clock speed.

104. The method of claim 103, wherein all said scan enable (SE) signals are used to switch said shift/compare and capture operation further comprises selectively operating a said scan enable (SE) signal in a selected clock domain at said selected clock domain?s rated clock speed, when a said capture clock controlling said selected clock domain contains one or more said second selected shift clock pulses, during each said capture operation.

105. The method of claim 103, wherein said providing two or more scan enable (SE) signals further comprises using a global scan enable (GSE) signal to drive one or more said scan enable (SE) signals, when the clock domains controlled by said one or more scan enable (SE) signals do not contain any said second selected shift clock pulse during each said capture operation;

wherein said global scan enable (GSE) signal is operated at a selected reduced clock speed.

106. The method of claim 101, wherein said generating and loading N predetermined stimuli to all said scan cells further comprises operating all said first selected shift clock pulses at selected clock speeds or at the same clock speed;

wherein all said first selected shift clock pulses are selectively skewed so that at any given time only one or more said scan cells are changing states to reduce power consumption.

107. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises applying said clock pulses concurrently to two or more selected clock domains which do not interact with each other or do not have any combinational logic block crossing each other, for detecting or locating said faults in said selected clock domains.

108. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises applying a reversed ordered sequence of clock pulses from said ordered sequence of clock pulses, for detecting or locating additional faults in said integrated circuit or circuit assembly.

109. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively applying a shortened or expanded ordered sequence of clock pulses from said ordered sequence of clock pulses, for detecting or locating additional faults in said integrated circuit or circuit assembly.

110. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises disabling all clock pulses in one or more capture clocks, to facilitate fault diagnosis.

111. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively operating all said clock pulses controlling a selected clock domain at a selected clock speed, for detecting or locating stuck-at faults within said selected clock domain.

112. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively operating all said clock pulses controlling a selected clock domain at their rated clock speed, for detecting or locating delay faults within said selected clock domain.

113. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively reducing the speed of all said clock pulses controlling a selected clock domain to the level, where delay faults associated with all multiple-cycle paths of equal cycle latency within said selected clock domain are detected or located at a predetermined rated clock speed.

114. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively operating all said clock pulses controlling two selected clock domains at selected clock speeds, for detecting or locating stuck-at faults crossing said two selected clock domains.

115. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively adjusting the relative clock delay of two said clock pulses controlling two selected clock domains, for detecting or locating delay faults crossing said two selected clock domains.

116. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises selectively adjusting the relative clock delay of two said clock pulses controlling two selected clock domains to the level, where delay faults associated with all multiple-cycle paths of equal cycle latency crossing said two selected clock domains are detected or located at a predetermined rated clock speed.

117. The method of claim 101, wherein said applying an ordered sequence of clock pulses further comprises controlling the relative clock delay between any two adjacent clock pulses inside or external to said integrated circuit or circuit assembly.

118. The method of claim 101, providing an automatic test equipment (ATE) and wherein said comparing N output responses directly with their expected output responses during a compare operation further comprises selectively comparing said N output responses directly with said expected output responses in said ATE.

119. The method of claim 101, wherein said comparing N output responses directly with their expected output responses during a compare operation further comprises selectively compacting said N output responses to signatures using a compact operation.

120. The method of claim 119, providing an automatic test equipment (ATE) and wherein said compacting said N output responses to signatures further comprises comparing said signatures with their expected signatures after a predetermined limiting criterion is reached;

wherein said comparing said signatures with their expected signatures further comprises selectively comparing said signatures inside said integrated circuit or circuit assembly, or shifting-out said signatures for comparison in said ATE.

121. The method of claim 101, wherein said scan cell is selectively a multiplexed D flip-flop or a level-sensitive scan latch, and further wherein said integrated circuit or circuit assembly under test is a full-scan or partial-scan design.

122. The method of claim 101, wherein said faults further comprise stuck-at faults and delay faults;

wherein said stuck-at faults further comprise other stuck-type faults, including open faults, IDDQ (IDD quiescent current) faults, and bridging faults, and wherein said delay faults further comprise other non-stuck-type delay faults, including transition (gate-delay) faults, multiple-cycle delay faults, and path-delay faults.

123. An apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly during scan-test, where N>

1, each clock domain having one or more capture clocks and one or more scan cells, each capture clock comprising a selected number of shift clock pulses and a selected number of capture clock pulses, each shift clock pulse comprising a clock pulse applied in scan mode, each capture clock pulse comprising a clock pulse applied in normal mode;

said apparatus comprising;

(a) a first hardware for generating and loading N predetermined stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly, by applying first selected shift clock pulses to all said scan cells in said scan mode for loading or shifting-in said N predetermined stimuli to all said scan cells, during a shift operation;

(b) a second hardware for applying an ordered sequence of clock pulses to all said scan cells within said N clock domains during a capture operation, the ordered sequence of clock pulses comprising at least a second selected shift clock pulse and a capture clock pulse from two or more selected capture clocks, for controlling two or more clock domains, in a sequential order, wherein one said selected capture clock must contain at least one said second selected shift clock pulse and the other said selected capture clock must contain at least one said capture clock pulse, and when detecting or locating selected delay faults within a clock domain, said selected capture clock controlling the clock domain selectively contains at least two consecutive capture clock pulses or a second selected shift clock pulse followed by at least one capture clock pulse to launch the transition and capture the output response; and

(c) a third hardware for comparing N output responses directly with their expected output responses for all said scan cells within said N clock domains and indicating errors immediately, by applying said first selected shift clock pulses to all said scan cells in said scan mode for comparing or shifting-out said N output responses for comparison with said expected output responses, during a compare operation.

124. The apparatus of claim 123, further comprising a fourth hardware for indicating errors after a predetermined limiting criterion is reached.

125. The apparatus of claim 123, further comprising a fifth hardware for programming each said capture clock to contain said ordered sequence of clock pulses, for performing said capture operation on all said scan cells within a selected clock domain controlled by said capture clock.

126. The apparatus of claim 123, providing an automatic test equipment (ATE) and wherein said first hardware for generating and loading N predetermined stimuli to all said scan cells further comprises a first additional hardware for loading and shifting-in said N predetermined stimuli to all said scan cells selectively within said integrated circuit or circuit assembly, or through said ATE.

127. The apparatus of claim 123, wherein said second hardware for applying an ordered sequence of clock pulses further comprises a second additional hardware for generating said ordered sequence of clock pulses during each said capture operation.

128. The apparatus of claim 123, providing an automatic test equipment (ATE) and wherein said third hardware for comparing N output responses directly with their expected output responses during a compare operation further comprises a third additional hardware for selectively comparing said N output responses directly with their expected output responses in said ATE.

129. The apparatus of claim 123, wherein said third hardware for comparing N output responses directly with their expected output responses during a compare operation further comprises a fourth additional hardware for selectively compacting said N output responses to signatures using a compact operation.

130. The apparatus of claim 129, providing an automatic test equipment (ATE) and wherein said fourth additional hardware for selectively compacting said N output responses to signatures further comprises a fifth additional hardware for comparing said signatures with their expected signature after a predetermined limiting criterion is reached;

wherein said fifth additional hardware for comparing said signatures with their expected signatures further comprises a sixth additional hardware for selectively comparing said signatures inside said integrated circuit or circuit assembly, or shifting-out said signatures for comparison in said ATE.

131. The apparatus of claim 123, wherein said scan cell is selectively a multiplexed D flip-flop or a level-sensitive scan latch, and further wherein said integrated circuit or circuit assembly under test is a full-scan or partial-scan design.

132. The apparatus of claim 123, wherein said faults further comprise stuck-at faults and delay faults;

wherein said stuck-at faults further comprise other stuck-type faults, including open faults, IDDQ (IDD quiescent current) faults, and bridging faults, and wherein said delay faults further comprise other non-stuck-type delay faults, including transition (gate-delay) faults, multiple-cycle delay faults, and path-delay faults.

133. The apparatus of claim 123, wherein each said hardware of (a)-(c) is selectively placed inside or external to said integrated circuit or circuit assembly.