System, apparatus and method for restricting data access

• US 20050235308A1
• Filed: 12/17/2004
• Published: 10/20/2005
• Est. Priority Date: 12/19/2003
• Status: Active Grant

• Current Assignee: Stmicroelectronics (Research & Development) Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Dellow, Andrew, Cordero, Rodrigo
• Granted Patent: US 8,191,125 B2
• Time in Patent Office: Days
• US Class Current: 725/25
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: H04N 21/4181 for conditional access
• CPC Class Codes: H04N 21/454 Content or additional data filtering, e.g. blocking advertisements
• CPC Class Codes: H04N 7/162 Authorising the user terminal, e.g. by paying; Registering the use of a subscription channel, e.g. billing

Abstract

An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.

Claims

1. A semiconductor integrated circuit for restricting a rate of data access from an external memory requested by one of one or more devices coupled to the semiconductor integrated circuit, comprising:

a data access monitor arranged to determine whether a data access from the external memory satisfies one or more conditions, and to generate an access signal according to whether the conditions are satisfied; and

a bandwidth comparator arranged to receive the access signal, and, if the access signal indicates that the data access satisfies the conditions, to determine a rate of data retrieval that satisfies the conditions, compare the rate of data retrieval with one or more thresholds, and to generate a threshold signal according to whether one or more of the thresholds have been exceeded to impair functioning of the semiconductor integrated circuit.

2. A semiconductor integrated circuit according to claim 1 wherein one of the conditions is that a device which is requesting the data is insecure.

3. A semiconductor integrated circuit according to claim 2 wherein the data access monitor further comprises:

a first memory for storing an indication of which devices are insecure; and

a first comparator for comparing an identification of a device which requested the data access with the indications of which devices are insecure, and arranged to generate a first condition signal to indicate whether the device requesting data is insecure.

4. A semiconductor integrated circuit according to claim 1 wherein one of the conditions is that requested data is privileged.

5. A semiconductor integrated circuit according to claim 4 wherein the external memory comprises two or more portions wherein each portion stores either privileged data or unprivileged data, and wherein the data access monitor further comprises:

a second memory for storing an indication of which portions of the external memory contain privileged data; and

a second comparator for comparing a location of a portion of retrieved data with those locations which contain privileged data, and arranged to generate a second condition signal to indicate whether the retrieved data portion is privileged.

6. A semiconductor integrated circuit according to claim 5 wherein the second memory is arranged to store start and end memory addresses of each portion of the external memory, and an indication of whether each portion stores privileged or unprivileged data.

7. A semiconductor integrated circuit according to claim 3 wherein the external memory comprises two or more portions wherein each portion stores either privileged data or unprivileged data, and wherein the data access monitor further comprises:

a second memory for storing an indication of which portions of the external memory contain privileged data; and

a second comparator for comparing a location of a portion of retrieved data with those locations which contain privileged data, and arranged to generate a second condition signal to indicate whether the retrieved data portion is privileged, wherein the data access monitor is further arranged to receive the first and second condition signals and to generate the access signal when the first and second condition signals indicate that the first and second conditions are satisfied.

8. A semiconductor integrated circuit according to claim 1 wherein the access signal comprises a stream of data portion signals, each data portion signal corresponding to a portion of data of a size being retrieved from the external memory.

9. A semiconductor integrated circuit according to claim 8 wherein each data portion signal comprises a one bit signal.

10. A semiconductor integrated circuit according to claim 8 wherein the bandwidth comparator is arranged to determine the rate of data retrieval by determining a frequency at which data portion signals are received.

11. A semiconductor integrated circuit according to claim 10 wherein the bandwidth comparator comprises:

a decrement block comprising a timer, the decrement block being arranged to periodically output a decrement signal at selected time intervals;

a bandwidth block having a first input that receives data portion signals from the data access monitor, and a second input that receives decrement signals from the decrement block, and comprising a bandwidth counter arranged to increment in value when a signal is received at the first input, and arranged to decrement when a signal is received at the second input; and

a monitoring block arranged to receive a current value of the bandwidth counter, to compare the value of the bandwidth counter with one or more thresholds, and to output a threshold signal according to whether one of the thresholds has been exceeded.

12. A semiconductor integrated circuit according to claim 1 wherein the bandwidth comparator is arranged to compare the rate of data retrieval with a first threshold and to impair data retrieval if the first threshold has been exceeded.

13. A semiconductor integrated circuit according to claim 12 wherein the bandwidth comparator is arranged to compare the rate of data retrieval with a second threshold which is lower than the first threshold, and to cause a warning to be conveyed to a user if the second threshold has been exceeded.

14. A semiconductor integrated circuit according to claim 12 wherein the first threshold is a value corresponding to a data retrieval rate of 200 kbits/second.

15. A semiconductor integrated circuit according to claim 1 wherein the bandwidth monitor is arranged to restrict the rate of data retrieval from the external memory if the device requesting the data is a processor.

16. A conditional access device for pay television, comprising:

a semiconductor integrated circuit for restricting a rate of data access from an external memory requested by one of one or more devices coupled to the semiconductor integrated circuit, the semiconductor integrated circuit including;

a data access monitor arranged to determine whether a data access from the external memory satisfies one or more conditions, and to generate an access signal according to whether the conditions are satisfied; and

a bandwidth comparator arranged to receive the access signal, and, if the access signal indicates that the data access satisfies the conditions, to determine a rate of data retrieval that satisfies the conditions, compare the rate of data retrieval with one or more thresholds, and to generate a threshold signal according to whether one or more of the thresholds have been exceeded to impair functioning of the semiconductor integrated circuit.

17. The conditional access device of claim 16 wherein one of the conditions is that a device which is requesting the data is secure.

18. The conditional access device of claim 17 wherein the data access monitor further comprises:

a first memory for storing an indication of which devices are secure; and

a first comparator for comparing an identification of a device which requested the data access with the indications of which devices are secure, and arranged to generate a first condition signal to indicate whether the device requesting data is secure.

19. The conditional access device of claim 16 wherein one of the conditions is that requested data is privileged.

20. A method for restricting the rate of data access requested by one of one or more devices from an external memory comprising the steps of:

monitoring data accesses from the external memory;

determining whether a monitored data access satisfies one or more conditions;

generating an access signal according to whether the conditions are satisfied;

determining a rate of data access satisfying the conditions;

comparing the rate of data access with one or more thresholds;

generating a threshold signal according to whether one or more of the threshold have been exceeded; and

impairing the functioning of the data access if one or more of the thresholds are exceeded.

21. The method according to claim 20 wherein a first condition is that a device which is requesting the data is insecure.

22. The method according to claim 21 further comprising the steps of:

receiving an identification of the device requesting the data;

comparing the device identification with one or more identifiers; and

determining that the first condition is satisfied if the device identification is identical to one of the identifiers.

23. The method according to claim 20 wherein a second condition is that a device has requested privileged data.

24. The method according to claim 23 further comprising the steps of:

receiving an identification of a location of data being retrieved from the external memory;

comparing the identified location with one or more memory locations; and

determining that the second condition is satisfied if the identified location falls within one of the memory locations.

25. The method according to claim 20 wherein generating an access signal further includes generating a stream of data portion signals, each data portion signal corresponding to a portion of data of a selected size being retrieved from the external memory that satisfies the conditions.

26. The method according to claim 25 wherein each data portion signal comprises a one bit signal.

27. The method according to claim 25 wherein determining the rate of data access further comprises determining the frequency at which data portion signals are received.

28. The method according to claim 25 wherein determining the rate of data access further comprises:

causing a counter to be incremented when a data portion signal is received; and

causing the counter to be decremented at a constant rate, wherein the counter value is indicative of the rate of data access.

29. The method according to claim 28, further comprising:

determining that the counter value exceeds a first threshold; and

causing a system reset if the first threshold is exceeded.

30. The method according to claim 29, further comprising the steps of:

determining that the counter value exceeds a second threshold wherein the second threshold is lower than the first threshold; and

presenting a warning to a user if the second threshold is exceeded;

31. The method according to claim 29 wherein the first threshold is a value corresponding to a data retrieval rate of 200 kbits/second.

32. A system for controlling access to a memory, the system comprising:

means for determining whether a received data request is from a secure device;

means for determining whether a rate of data exceeds a first threshold; and

means for restricting access to the memory communicatively coupled to the means for determining whether a received data request is from a secure device and the means for determining whether a rate of data exceeds a first threshold.

33. The system of claim 32, further comprising means for preventing receipt of illegitimate signals by the means for determining whether a received data request is from a secure device, the means for determining whether a rate of data exceeds a first threshold and the means for restricting access to the memory.

34. The system of claim 33 wherein the means for preventing receipt of illegitimate signals comprises a monolithic integrated semiconductor circuit.

35. The system of claim 32, wherein the means for determining whether a received data request is from a secure device, the means for determining whether a rate of data exceeds a first threshold and the means for restricting access to the memory are integrated into a monolithic semiconductor.

36. The system of claim 32, further comprising means for determining whether a received data request is directed to privileged data.

37. The system of claim 32 wherein the means for determining whether a received data request is from a secure device comprises a data access monitor.

38. The system of claim 37 wherein the data access monitor comprises a first memory, a first comparator and a signal generator.

39. The system of claim 32 wherein the means for determining whether a rate of data exceeds a first threshold comprises a bandwidth comparator.

40. The system of claim 32 wherein the means for restricting access to the memory comprises a data blocking device.

41. The system of claim 32, further comprising means for decrypting encoded data.

42. A method of controlling access to a memory, comprising:

receiving a request to access data in the memory;

determining whether the request is from an authorized device;

processing a request from an authorized device;

monitoring a data rate associated with the processing; and

controlling the access in response to the monitoring.

43. The method of claim 42 wherein determining whether the request is from an authorized device comprises:

identifying a requesting device; and

determining whether the identified device is on a list of authorized devices.

44. The method of claim 43 wherein determining whether the request is from an authorized device further comprises:

determining whether the request is directed to privileged data; and

determining whether the device is authorized to receive privileged data.

45. The method of claim 42, further comprising:

determining a type of an authorized device; and

controlling the access in response to the determination of the type of the authorized device.

46. A computer readable media containing instructions for causing a memory controller to:

determine whether a received request to access a memory is from an authorized device;

process a request from an authorized device;

monitor a data rate associated with the processing; and

control access to the memory in response to the monitoring.

47. The computer readable media of claim 46 wherein the instructions cause the memory controller to determine whether a request is directed to privileged data.

48. The computer readable media of claim 46 wherein the instructions cause the memory controller to determine a type of an authorized device and to control access to the memory based on the determined type.