Method of manufacturing a semiconductor device and semiconductor device obtainable with such a method

• US 20050236663A1
• Filed: 03/11/2005
• Published: 10/27/2005
• Est. Priority Date: 03/12/2004
• Status: Active Grant

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International), NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Pawlak, Bartlomiej Jan
• Granted Patent: US 7,326,620 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of manufacturing a semiconductor device comprising a dual gate field effect transistor is disclosed, in which method a semiconductor body with a surface and of silicon is provided with a source region and a drain region of a first conductivity type and with a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region and with a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region and with a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, and wherein both gate regions are formed within a trench formed in the semiconductor body.

Claims

1. A method of manufacturing a semiconductor device comprising a dual gate field effect transistor, comprising:

providing a semiconductor body of silicon with a surface, a source region and a drain region of a first conductivity type, a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

forming a first gate region within a first trench, separated from the channel region by a first gate dielectric and situated on one side of the channel region;

forming a second gate region within a second trench, separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region,

wherein both gate regions are formed within a trench formed in the semiconductor body,

wherein the channel region is formed by the part of the semiconductor body between the first and second trench, and

wherein the source and drain regions are formed at the surface of the semiconductor body.

2. The method as claimed in claim 1, wherein the two trenches are formed in parallel in the surface of the semiconductor body and the trench walls are provided with a dielectric layer and are filled with a conductive material by depositing a conductive layer on the semiconductor body, and wherein selected portions on top of the surface of the semiconductor body are removed by chemical mechanical polishing.

3. The method as claimed in claim 1, wherein the source and drain regions are formed by depositing a strip-shaped mask layer on the surface of the semiconductor body which bridges the two regions where the trenches are formed or to be formed, after which dopants of the first conductivity type are introduced into the semiconductor body on both sides of the strip-shaped mask layer.

4. The method as claimed in claim 1, wherein the source and drain regions are formed by implantation.

5. The method as claimed in claim 1, further comprising forming two dual gate transistors which are proximate each other in the semiconductor body by forming a third trench in the semiconductor body of which the middle trench forms a common gate region for the two dual gate transistors.

6. The method as claimed in claim 5, wherein a first of the two dual gate transistors is formed as an npn transistor and a second of the two dual gate transistors is formed as a pnp transistor.

7. The method as claimed in claim 1, wherein the source and drain regions of the dual gate transistor are separated from the semiconductor body on a side opposite to the channel region by further trenches.

8. The method as claimed in claim 1, wherein the dual gate transistor is formed together with other conventional transistors made by conventional CMOS technology.

9. The method as claimed in claim 2, wherein the conductive layer comprises metal.

10. A semiconductor device comprising a dual gate field effect transistor, wherein the dual gate field effect transistor comprises:

a semiconductor body with a surface and comprising silicon;

a source region and a drain region of a first conductivity type;

a channel region of a second conductivity type, opposite to the first conductivity type, between the source region and the drain region;

a first gate region separated from the channel region by a first gate dielectric and situated on one side of the channel region, wherein the first gate region is formed within a first trench;

a second gate region separated from the channel region by a second gate dielectric and situated on an opposite side of the channel region, wherein the second gate region is formed within a second trench, wherein both gate regions are formed within a trench formed in the semiconductor body, and wherein the channel region is formed by the part of the semiconductor body between the first and second trench and the source and drain regions are formed at the surface of the semiconductor body.

11. The semiconductor device as claimed in claim 10, further comprising a second neighboring dual gate transistor with one gate region in common to both transistors.