Semiconductor device and method of manufacturing thereof

• US 20050236664A1
• Filed: 04/21/2005
• Published: 10/27/2005
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tsuzuki, Yukio, Aoki, Takaaki, Shiga, Tomofusa, Suzuki, Mikimasa
• Granted Patent: US 7,622,768 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

On the surface of a silicon nitride film, there is formed a thermal oxide film, over which a CVD oxide film is then formed to provide a silicon oxide film of two-layered structure films. Moreover, the total thickness of the two-layered structure films is set to a value from 5 nm to 30 nm. Thus, the silicon oxide film is made into the two-layered structure films of the thermal oxide film and the CVD oxide film to thereby achieve the thickness of the silicon oxide film. As a result, it is possible to prevent a Vth from being lowered by a charge trap phenomenon and to prevent the Vth from fluctuating due to the enlargement of the bird'"'"'s beak length by the silicon oxide film.

Claims

1. A semiconductor device comprising a semiconductor element having an insulated gate structure, in which a gate insulating film having an ONO film comprised of a first silicon oxide film, a silicon nitride film and a second silicon oxide film is formed on the side face of a trench formed on one face of a semiconductor substrate, and in which a gate electrode is formed on the surface of said gate insulating film in said trench, characterized:

in that said second silicon oxide film comprises a two-layered structure films including;

either a thermal oxide film formed on the surface of said silicon nitride film and a CVD oxide film formed over said thermal oxide film;

or a CVD film formed on the surface of said silicon nitride film and a thermal oxide film formed over said CVD film; and

in that a total thickness of said two-layered structure films is set to a value from 4 nm to 30 nm.

2. A semiconductor device as in claim 1, characterized in that a thickness of said second silicon oxide film is set to a value from 5 nm to 30 nm.

3. A semiconductor device as in claim 1, characterized in that a thickness of said second silicon oxide film is set to a value from 4 nm to 10 nm.

4. A semiconductor device as set forth in claim 1, characterized in that, in case said semiconductor element is an n-channel type element, a thickness of said second silicon oxide film is set to a value from 5 nm to 10 nm.

5. A semiconductor device as set forth in claim 1, characterized in that, in case said semiconductor element is a p-channel type element, a thickness of said second silicon oxide film is set to a value from 4 nm to 6 nm.

6. A semiconductor device as set forth in claim 2, characterized in that, in case said semiconductor element is an IGBT, said second silicon oxide film is made to have said thermal oxide film set to a thickness from 2.5 nm to 6 nm and to have a remaining portion made of said CVD oxide film.

7. A semiconductor device as set forth in claim 2, characterized in that, in case said semiconductor element is a MOS transistor, said second silicon oxide film is made to have said thermal oxide film set to a thickness from 1.5 nm to 4 nm and to have a remaining portion made of said CVD oxide film.

8. A semiconductor device as set forth in claim 1, characterized in that said gate insulating film is made such that it is made of said ONO film only on the side face of said trench but made of silicon oxide films in the upper portion and in the bottom portion of said trench, and such that the silicon oxide films positioned in the upper portion and in the lower portion of said trench are made thicker than that of the ONO film positioned on the side face of said trench.

9. A method for manufacturing a semiconductor device comprising a semiconductor element having an insulated gate structure, in which a gate insulating film having an ONO film composed of a first silicon oxide film, a silicon nitride film and a second silicon oxide film is formed on the side face of a trench formed on one face of a semiconductor substrate, and in which a gate electrode is formed on the surface of said gate insulating film in said trench, characterized:

in that the step of forming said second silicon oxide film includes;

the step of forming a thermal oxide film on the surface of said silicon nitride film; and

the step of forming a CVD oxide film over said thermal oxide film;

in that said second silicon oxide film is made of two-layered structure films including;

said thermal oxide film and said CVD oxide film; and

in that the thicknesses of said thermal oxide film and said CVD oxide film are made such that the total thickness of said two-layered structure films is set to a value from 5 nm to 30 nm.

10. A method for manufacturing a semiconductor device comprising a semiconductor element having an insulated gate structure, in which a gate insulating film having an ONO film comprised of a first silicon oxide film, a silicon nitride film and a second silicon oxide film is formed on the side face of a trench formed on one face of a semiconductor substrate, and in which a gate electrode is formed on the surface of said gate insulating film in said trench, characterized:

in that the step of forming said second silicon oxide film includes;

the step of forming a CVD oxide film on the surface of said silicon nitride film; and

the step of forming a thermal oxide film over said CVD oxide film;

in that said second silicon oxide film is made of two-layered structure films including;

said thermal oxide film and said CVD oxide film; and

in that the thicknesses of said thermal oxide film and said CVD oxide film are made such that the total thickness of said two-layered structure films is set to a value from 5 nm to 30 nm.