Silicon oxycarbide and silicon carbonitride based materials for MOS devices

• US 20050236694A1
• Filed: 07/21/2004
• Published: 10/27/2005
• Est. Priority Date: 04/27/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, H. C., Liang, Mong Song, Lin, Da-Wen, Wu, Zhen-Cheng, Chang, Weng, Cheng, Shwang-Ming
• Granted Patent: US 7,115,974 B2
• Time in Patent Office: Days
• US Class Current: 257/632
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/314 Inorganic layers H01L21/3105, H01L21/32 take precedence
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19041 being a capacitor

Abstract

In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.

Claims

1. An integrated circuit device comprising:

a substrate having a surface;

a gate dielectric formed on the surface of the substrate;

a gate electrode formed on the gate dielectric;

a pair of spacers formed along opposite sidewalls of the gate electrode and the gate dielectric;

source and drain regions formed on opposite sides of the gate electrode;

a contact etch stop (CES) layer blanket formed on the source and drain regions and the spacers wherein the CES layer is formed of a material selected from the group consisting essentially of a silicon oxycarbide (SiCO) based material and a silicon carbonitride (SiCN) based material;

an inter-level dielectric (ILD) formed on the CES layer; and

a conductive plug formed in the inter-level dielectric.

2. The integrated circuit device of claim 1 wherein the spacer material is a material selected from the group consisting essentially of a Silicon, Carbon containing based oxide and a Silicon, Carbon containing based nitride and having a dielectric constant (k value) smaller than about 5.0.

3. The integrated circuit device of claim 1 further comprising a glue layer formed on the CES layer.

4. The integrated circuit device of claim 3 wherein the glue layer material is SiC.

5. The integrated circuit device of claim 3 wherein the glue layer has a thickness of about 20 Å

to about 50 Å

.

6. The integrated circuit device of claim 1 wherein the CES layer has a k value less than about 7.0.

7. The integrated circuit device of claim 1 wherein the thickness of the CES layer is between about 1000 Å

to about 1000 Å

.

8. The integrated circuit device of claim 1 wherein the CES layer has an inherent stress between about −

3GPa and 3GPa.

9. The integrated circuit device of claim 1 further comprising a step feature comprising a material selected from the group consisting essentially of a Silicon, Carbon containing based oxide and a Silicon, Carbon containing based nitride and having a k value less than about 5.0.

10. The integrated circuit device of claim 9 wherein the step feature has a height greater than about 300 Å

.

11. The integrated circuit device of claim 9 wherein the step feature has an aspect ratio greater than about 2.

12. The integrated circuit device of claim 9 further comprising:

a second gate electrode formed over a second gate dielectric and having a second pair of spacers formed along opposite sidewalls of the gate electrode and the gate dielectric, wherein one of the spacers of the second pair of spacers is spaced apart from one of said pair of spacers by at most 300 Å

.

13. The integrated circuit device of claim 1 wherein the ILD material comprises a material selected from the group consisting essentially of a Silicon, Carbon containing based oxide and a Silicon, Carbon containing based nitride.

14-26. -26. (canceled)

27. An integrated circuit device comprising:

a gate dielectric on a surface of a substrate;

a gate electrode on the gate dielectric;

a spacer along a sidewall of the gate electrode and the gate dielectric;

a source/drain region adjacent the spacer;

a contact etch stop (CES) layer over the source/drain region and the spacer wherein the CES layer comprises a material selected from the group consisting essentially of a silicon oxycarbide (SiCO) based material and a silicon carbonitride (SiCN) based material;

an inter-level dielectric (ILD) on the CES layer; and

a conductor in the inter-level dielectric.

28. The method of claim 27 further comprising a SiC glue layer underlying the CES layer.

29. The integrated circuit device of claim 27 wherein the CES layer has an inherent stress between about −

3GPa to about 3GPa.

30. The integrated circuit device of claim 27 wherein the spacer material is a material selected from the group consisting essentially of a SiCO based material and a SiCN based material and wherein the spacer material has a k value less than about 5.0.

31. The integrated circuit device of claim 27 further comprising step features wherein the step features material is SiCO or SiCN based material having a k value smaller than about 5.0.

32. The integrated circuit device of claim 27 further comprising:

at least two transistor devices having spacers wherein the spacing between the spacer of the first transistor device and the spacer of the second transistor device is smaller than about 300 Å

.