Intelligent probe card architecture

• US 20050237073A1
• Filed: 04/21/2004
• Published: 10/27/2005
• Est. Priority Date: 04/21/2004
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Miller, Charles A., Henson, Roy J., Chraft, Matthew E.
• Granted Patent: US 7,307,433 B2
• Time in Patent Office: Days
• US Class Current: 324/756.30
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.

Claims

1-3. -3. (canceled)

4. A probe card assembly comprising a programmable controller to control the provision of test signals to test probes of the probe card for testing components on a wafer, wherein the programmable controller is connected through an interface to a test system controller, where the test system controller provides test signals to the interface to control testing of components on a wafer, wherein the interface comprises one or more of a group consisting of a parallel, wireless, network, RF and IR interface.

5. (canceled)

6. A probe card assembly comprising a programmable controller to control the provision of test signals to test probes of the probe card for testing components on a wafer, wherein the programmable controller comprises a serial to parallel converter configured to receive the test signals, the programmable controller configured to convert the test signals from serial to parallel and distribute the test signals in parallel to the test probes.

7. A probe card assembly comprising a programmable controller to control the provision of test signals to test probes of the probe card for testing components on a wafer, wherein programmable controller is configured to perform self testing of components included in the probe card assembly.

8. A probe card assembly comprising:

a programmable controller to control the provision of test signals to test probes of the probe card for testing components on a wafer; and

a serial to parallel converter connected to receive signals from the programmable controller, the serial to parallel converter being configured to convert the test signals from serial to parallel and distribute the test signals in parallel to the test probes.

9. The probe card assembly of claim 8, wherein the serial to parallel converter comprises a serial digital to analog converter connected to receive digital test signals from the programmable controller, the digital to analog converter configured to convert the serial signals to parallel and to provide the test signals to the test probes in analog form.

10-24. -24. (canceled)

27. A probe card assembly comprising:

a DC-DC converter connected between the single power supply line of a test system controller, the power supply line distributing power through line branches to multiple test probes, the DC-DC converter configured to increase current in a signal provided on the power supply line; and

power supply isolation devices connected in series with the line branches, wherein the power supply isolation devices are configured to minimize current flow on a given one of the power supply line branches when a DUT on the given line is determined to be faulty.

25. The probe card assembly of claim 27, wherein the power supply isolation devices comprise one or more of a group consisting of voltage regulators, switches and current limiters.

26. The probe card assembly of claim 27 comprising:

a space transformer supporting the test probes;

at least one daughter card; and

a base PCB electrically interconnected with the space transformer and the at least one daughter card, wherein the power supply isolation devices are provided on at least one of the space transformer, the base PCB, and the at least one daughter card.

28. A probe card assembly comprising a programmable controller configured to perform self testing of components included in the probe card assembly.

29. A probe card assembly comprising a serial interface device configured to connect to a test system controller to receive test signals for distributing to probes of the probe card assembly.

30. The probe card assembly of claim 29, further comprising:

a serial to parallel converter for converting the test signals from serial to parallel and distributing the test signals in parallel to a plurality of test probes.

31. The probe card assembly of claim 30, wherein the serial to parallel converter comprises a Field Programmable Gate Array (FPGA).

32. The probe card assembly of claim 31 comprising:

a space transformer supporting the test probes;

at least one daughter card; and

a base PCB electrically interconnected with the space transformer and the at least one daughter card, wherein the serial to parallel converter is provided on at least one of the space transformer, the base PCB, and the at least one daughter card.

33. A probe card assembly comprising:

a serial digital to analog converter configured to serially receive digital test signals that are to be distributed to test probes of the probe card in analog form, the digital to analog converter configured to convert the test signals to parallel and to provide the test signals to the test probes in analog form.

34. The probe card assembly of claim 33, further comprising:

an analog to digital converter configured to receive an analog signal from a test device and to send a digital representation to a test system controller.

35. The probe card assembly of claim 34 comprising:

a space transformer supporting the test probes;

at least one daughter card; and

a base PCB electrically interconnected with the space transformer and the at least one daughter card, wherein the serial digital to analog converter and the analog to digital converter are each provided on at least one of the space transformer, the base PCB, and the at least one daughter card.

36. A probe card assembly comprising a programmable controller to control the provision of test signals to test probes of the probe card for testing components on a wafer, wherein the programmable controller is connected through a wireless interface to a test system controller, where the test system controller provides test signals to the wireless interface to control testing of components on a wafer.

37. A method for testing DUTs using a probe card assembly, the probe card assembly including a base PCB with connectors for removably connecting at least one daughter card, the base PCB further including connectors for connecting to a test system controller and routing lines from the connectors to contacts providing electrical connections to test probes for contacting DUTs, the method comprising:

connecting a first one of the daughtercards to the PCB of the probe card, the first daughtercard configured to apply signals for testing a first group of DUTs;

testing the first group of the DUTs using signals applied from the first daughtercard through the test probes of the probe card to the first group of DUTs;

disconnecting the first daughtercard from the probe card;

connecting a second one of the daughtercards to the PCB of the probe card, the second daughtercard configured to apply signals for testing a second group of DUTs; and

testing the second group of the DUTs using signals applied from the second daughtercard through the test probes of the probe card to the first group of DUTs.