Integrated circuit output driver circuitry with programmable preemphasis

• US 20050237082A1
• Filed: 06/07/2005
• Published: 10/27/2005
• Est. Priority Date: 01/07/2003
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Patel, Rakesh H., White, Thomas H., Shumarayev, Sergey Y.
• Granted Patent: US 7,109,743 B2
• Time in Patent Office: Days
• US Class Current: 326/26
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834

Abstract

Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Claims

1-15. -15. (canceled)

16. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable pulse generator circuitry that is programmed to adjust the duration of the preemphasis;

programmable current supply circuitry that is programmed to adjust the magnitude of preemphasis; and

preemphasis driver circuitry coupled to the programmable pulse generator circuitry and the programmable current supply circuitry for producing the preemphasis.

17. The preemphasis circuitry of claim 16, wherein the programmable pulse generator circuitry comprises a delay circuit that is programmed to adjust the duration of the preemphasis.

18. The preemphasis circuitry of claim 16, wherein the programmable pulse generator circuitry comprises a pulse generator.

19. The preemphasis circuitry of claim 16, wherein the programmable pulse generator circuitry further comprises a function control element that is programmed to adjust the duration of the preemphasis.

20. The preemphasis circuitry of claim 16, wherein the programmable current supply circuitry comprises a function control element that is programmed to adjust the magnitude of preemphasis.

21. The preemphasis circuitry of claim 16, wherein the preemphasis circuitry is configured to provide preemphasis for different high-speed differential I/O signaling standards.

22. The preemphasis circuitry of claim 21, wherein the different high-speed differential I/O signaling standards include at least one signaling standard selected from the group of standards consisting of LVPECL, LVDS, and PCML.

23. The preemphasis circuitry of claim 16, further comprising programmable circuitry that is programmed to adjust how much slope steepening is provided by the preemphasis driver circuitry.

24. A programmable logic device integrated circuit comprising:

main differential driver circuitry that produces differential digital output data signals across a pair of output lines; and

the preemphasis circuitry of claim 16 for providing preemphasis to the differential digital output data signals.

25. Preemphasis circuitry for providing preemphasis to differential digital output data signals, comprising:

programmable current supply circuitry, wherein the magnitude of preemphasis is adjusted by the programmable current supply circuitry; and

preemphasis driver circuitry coupled to the programmable current supply circuitry for producing the preemphasis.

26. The preemphasis circuitry of claim 25, further comprising programmable pulse generator circuitry coupled to the preemphasis driver circuitry that is programmed to adjust the duration of the preemphasis.

27. The preemphasis circuitry of claim 26, wherein the programmable pulse generator circuitry comprises a delay circuit that is programmed to adjust the duration of the preemphasis.

28. The preemphasis circuitry of claim 26, wherein the programmable pulse generator circuitry comprises a pulse generator.

29. The preemphasis circuitry of claim 26, wherein the programmable pulse generator circuitry further comprises a function control element that is programmed to adjust the duration of the preemphasis.

30. The preemphasis circuitry of claim 25, wherein the programmable current supply circuitry comprises a function control element that is programmed to adjust the magnitude of preemphasis.

31. The preemphasis circuitry of claim 25, wherein the preemphasis circuitry is configured to provide preemphasis for different high-speed differential I/O signaling standards.

32. The preemphasis circuitry of claim 25, wherein the different high-speed differential I/O signaling standards include at least one signaling standard selected from the group of standards consisting of LVPECL, LVDS, and PCML.

33. The preemphasis circuitry of claim 25, further comprising programmable circuitry that is programmed to adjust how much slope steepening is provided by the preemphasis driver circuitry.

34. A programmable logic device integrated circuit comprising:

main differential driver circuitry that produces differential digital output data signals across a pair of output lines; and

the preemphasis circuitry of claim 25 for providing preemphasis to the differential digital output data signals.