Charge pump circuit reducing noise and charge error and PLL circuit using the same

• US 20050237092A1
• Filed: 04/18/2005
• Published: 10/27/2005
• Est. Priority Date: 04/27/2004
• Status: Active Grant

• Current Assignee: Seiko NPC Corporation (Seiko Group)
• Original Assignee: Seiko NPC Corporation (Seiko Group)
• Inventors: Otsuka, Haruhiko, Kawago, Hiroshi
• Granted Patent: US 7,271,619 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/0896 the current generators being controlled by differential up-down pulses
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64. The transistor P1 is turned on and off by an up-signal of the phase comparison circuit 34, and the transistor N1 is turned on and off by a down-signal of it, and each of the transistor P2, the transistor P3, the transistor N2 and the transistor N3 is turned on and off on the basis of the control signal of the control circuit 35, an output signal from a VCO control terminal 65 is input to a VCO 8 through a low pass filter 37 while causing current to flow through the charge pump circuit 36.

Claims

1. A charge pump circuit comprising:

a first P-channel MOS transistor having a source, a drain connected to an output terminal and a gate receiving a first signal;

a first N-channel MOS transistor having a source, a drain connected to the output terminal and a gate receiving a second signal;

a second P-channel MOS transistor having a source connected to the source of the first P-channel MOS transistor, a drain and a gate receiving an inverted signal of the first signal;

a second N-channel MOS transistor having a source connected to the source of the first N-channel MOS transistor, a drain and a gate receiving an inverted signal of the second signal;

a first current source for providing a current of first level to the source of the first P-channel MOS transistor;

a second current source for providing a current of second level to the source of the first N-channel MOS transistor;

a third current source for providing a current of third level to the drain of the second N-channel MOS transistor; and

a fourth current source for providing a current of fourth level to the drain of the second P-channel MOS transistor.

4. A phase-locked loop circuit having the charge pump circuit according to any one of claims 1 to 3 for outputting a current depending on output signals of the control circuit and the phase comparison circuit, comprising:

a voltage controlled oscillator circuit for outputting a signal depending on the voltage level of an input signal;

a reference signal source for generating a reference signal;

a first frequency division circuit for dividing a frequency of the reference signal;

a second frequency division circuit for dividing a frequency of the signal of the voltage controlled oscillator circuit;

the phase comparison circuit for comparing the phase of output signals of both the frequency division circuits to output an up-signal and a down-signal, and for detecting a lock state to output the lock detected signal;

the control circuit for outputting the control signal depending on the output signal of the phase comparison circuit; and

a low pass filter for attenuating a high frequency component of an output signal of the charge pump circuit to pass only a low frequency component of the output signal to the voltage controlled oscillator circuit.

2. A charge pump circuit for providing an output through a first output terminal to a low pass filter having a resistor and a first capacitance that are connected in series between the first output terminal and a ground terminal, and a second capacitance connected in parallel to the first capacitance between the first output terminal and the ground terminal, comprising:

a first P-channel MOS transistor having a source, a drain connected to the first output terminal and a gate receiving a first signal;

a first N-channel MOS transistor having a source, a drain connected to the first output terminal and a gate receiving a second signal;

a third P-channel MOS transistor having a source, a drain connected to a second output terminal which is connected between the resistor and the first capacitance, and a gate receiving the first signal;

a third N-channel MOS transistor having a source, a drain connected to the second output terminal and a gate receiving the second signal;

a first current source for providing a current of first level to the source of the first P-channel MOS transistor;

a second current source for providing a current of second level to the source of the first N-channel MOS transistor;

a third current source for providing a current of third level to the source of the third P-channel MOS transistor; and

a fourth current source for providing a current of fourth level to the source of the third N-channel MOS transistor.

3. A charge pump circuit for receiving a control signal depending on an output of a phase comparison circuit from a control circuit that receives a first signal, a second signal and a lock detected signal of the phase comparison circuit output while a phase-locked loop circuit being in the lock state, comprising:

a first P-channel MOS transistor having a source, a drain connected to a first output terminal and a gate receiving the first signal;

a first N-channel MOS transistor having a source, a drain connected to the first output terminal and a gate receiving the second signal;

a second P-channel MOS transistor having a source connected to the source of the first P-channel MOS transistor, a drain and a gate receiving an inverted signal of the first signal while the lock detected signal being provided;

a second N-channel MOS transistor having a source connected to the source of the first N-channel MOS transistor, a drain and a gate receiving an inverted signal of the second signal while the lock detected signal being provided;

a third P-channel MOS transistor having a source connected to the drain of the second N-channel MOS transistor, a drain connected to a second output terminal and a gate receiving the first signal while the lock detected signal being not provided;

a third N-channel MOS transistor having a source connected to the drain of the second P-channel MOS transistor, a drain connected to the second output terminal and a gate receiving the second signal while the lock detected signal being not provided;

a first current source for providing a current of first level to the source of the first P-channel MOS transistor;

a second current source for providing a current of second level to the source of the first N-channel MOS transistor;

a third current source for providing a current of third level to the drain of the second N-channel MOS transistor; and

a fourth current source for providing a current of fourth level to the drain of the second P-channel MOS transistor;