Method and circuit arrangement for load modulation in a combination comprised of a transmitting and a receiving oscillator circuit

• US 20050237123A1
• Filed: 04/22/2005
• Published: 10/27/2005
• Est. Priority Date: 04/22/2004
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Schneider, Peter, Berhorst, Martin
• Granted Patent: US 7,319,368 B2
• Time in Patent Office: Days
• US Class Current: 331/117.R
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H03C 1/14 the element being a diode

Abstract

A method and circuit arrangement is provided for load modulation in a receiving oscillator circuit, which can be mutually coupled with a transmitting oscillator circuit, having at least one inductance, at least one capacitance, and at least one controllable impedance. The controllable impedance can have at least one depletion layer element and at least one ohmic resistance.

Claims

1. A method for load modulation in a system comprising a transmitting oscillator circuit and a receiving oscillator circuit, the method comprising the steps of:

modulating a voltage in the transmitting oscillator circuit by retroaction of a voltage alteration in the receiving oscillator circuit; and

controllably changing a load modulation of an impedance of the receiving oscillator circuit that includes at least one depletion layer element and at least one ohmic resistance.

2. The method according to claim 1, wherein the changing of the impedance of the receiving oscillator circuit is performed by controlled bridging of the at least one depletion layer element and/or the at least one ohmic resistance.

3. A circuit arrangement for load modulation in a receiving oscillator circuit, which can be mutually coupled with a transmitting oscillator circuit, the circuit arrangement comprising:

at least one inductor;

at least one capacitor; and

a controllable impedance including at least one depletion layer element and at least one ohmic resistance.

4. The circuit arrangement according to claim 3, wherein the controllable impedance is located between a first oscillator circuit connection and a reference potential connection.

5. The circuit arrangement according to claim 4, wherein the controllable impedance includes a first controllable impedance between the first oscillator circuit connection and the reference potential connection, and includes a second controllable impedance between a second oscillator circuit connection and the reference potential connection.

6. The circuit arrangement according to claim 5, wherein an arrangement and structure of the first controllable impedance and the second controllable impedance is symmetric to the reference potential connection.

7. The circuit arrangement according to claim 3, wherein the controllable impedance further includes a switchable bypass formed of at least one depletion layer element and/or the ohmic resistance.

8. The circuit arrangement according to claim 7, wherein the switchable bypass includes an operating current path of a transistor.

9. The circuit arrangement according to claim 3, wherein the controllable impedance further includes at least one series connection of a first depletion layer element and the ohmic resistance.

10. The circuit arrangement according to claim 9, wherein, in addition to the first depletion layer element, the series connection further includes at least one second depletion layer element, which is in series with the first depletion layer element and has a forward direction that is opposite a forward direction of the first depletion layer element.

11. The circuit arrangement according to claim 10, wherein the second depletion layer element is a Zener diode.

12. The circuit arrangement according to claim 3, wherein the controllable impedance includes a parallel connection formed of at least one semiconductor component and at least one ohmic resistance.

13. The circuit arrangement according to claim 12, wherein the semiconductor component is a diode.

14. The circuit arrangement according to claim 12, wherein the semiconductor component is a transistor, which is controlled by a voltage drop in the ohmic resistance, and includes an operating current path that at least bridges the ohmic resistance.

15. The circuit arrangement according to claim 14, wherein the operating current path of the transistor is between an oscillator circuit connection and a reference potential connection.