Write driver with improved boosting circuit and interconnect impedance matching

• US 20050237785A1
• Filed: 04/13/2005
• Published: 10/27/2005
• Est. Priority Date: 04/14/2004
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Venca, Alessandro, Alini, Roberto, Posat, Baris
• Granted Patent: US 7,365,928 B2
• Time in Patent Office: Days
• US Class Current: 365/154
• CPC Class Codes: G11B 2005/0018 by current biasing control or regulation
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: G11B 5/022 H-Bridge head driver circuit, the "H" configuration allowing to inverse the current direction in the head
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a pair of current sources, such as MOS transistors, connected to the input node of a single capacitor. During the overshoot duration, the current sources selectively operate at saturation to generate a pulsed current with an amplitude of half the load current. The recharge of the capacitor is done with the load current.

Claims

1. A write driver circuit for driving current through a write head in a hard disk system, the driver being adapted to have an improved output dynamic range, the write driver comprising:

an output node for connecting with an interconnect to the write head;

means for receiving a supply voltage;

a pair of current generators connected to the supply voltage receiving means and generating a pulsed current; and

a capacitance device with an input node and an output node, the input node being connected to the current generators, wherein the capacitance device output node is connected to the write driver circuit output node, whereby the pulsed current flows through the capacitance device to the write driver circuit output node.

2. The write driver circuit of claim 1, further comprising means for receiving a charging voltage and means for selectively applying after an overshoot duration the charging voltage to the input node of the capacitance device to pre-charge the capacitance device.

3. The write driver circuit of claim 1, wherein the pulsed current is provided by the capacitance device for a period of time equal to an overshoot duration and wherein the capacitance device comprises a capacitor with a capacitance large enough to avoid saturation of the current generator during the time period.

4. The write driver circuit of claim 1, further comprising a bias circuit periodically applying a bias voltage to the output node of the capacitance device.

5. The write driver circuit of claim 4, wherein the bias circuit comprises a transistor coupled to a voltage source and connected to the output node of the capacitance device.

6. The write driver circuit of claim 1, further comprising an impedance matching circuit connected to the output node of the write driver circuit, the impedance matching circuit comprising a resistor having a resistance substantially equal to the odd character impedance of the interconnect to the write head.

7. The write driver circuit of claim 6, wherein the impedance matching circuit further comprises means for generating a voltage pulse to the resistor, the voltage pulse having an amplitude substantially equal to an output voltage at the output node of the write driver circuit, whereby the pulsed current is blocked from flowing through the resistor.

8. The write driver circuit of claim 6, wherein the impedance matching circuit further comprises a voltage source comprising a buffer with unity gain connected to the resistor on a side distal to the write driver circuit output node.

9. A write assembly for a hard disk drive storing data on a disk, comprising:

a write head with a coil writing data to a surface of the disk in response to a write current passing through the coil;

an electrical interconnect connected to the write head coil, the interconnect comprising a transmission line having an odd characteristic impedance; and

a write driver with an output node connected to the interconnect, the write driver generating a pulsed current to drive the write current through the coil,

wherein the write driver comprises a boosting circuit comprising means for receiving a supply voltage having a first amplitude and means for boosting the supply voltage to apply an output voltage at the output node with a second amplitude greater than the first amplitude,

the boosting circuit comprising a pair of current generators connected to the supply voltage receiving means and generating a pulsed current and a capacitance device with an input node and an output node, the input node being connected to the current generators, wherein the capacitance device output node is connected to the output node;

wherein the write current has an amplitude about twice an amplitude of the pulsed current; and

wherein the write driver comprises an impedance matching circuit setting an output resistance of the write driver to about the odd characteristic impedance of the interconnect.

10. The write assembly of claim 9, the boosting circuit further comprising a first transistor and a second transistor connected in parallel to the capacitor output node adapted to periodically apply a voltage to the capacitor output node.

11. The write assembly of claim 10, wherein the current generators each comprise a transistor selectively operated for an overshoot duration to provide the pulsed current, wherein the amplitude of the pulsed current is substantially constant during the overshoot duration, and wherein the capacitor has a size selected to maintain the current generator transistor from becoming saturated during the overshoot duration.

12. A write driver for selectively providing a write current through a write head, the write driver being connected to the write head by an interconnect with an odd characteristic impedance, the write driver comprising:

an impedance matching device connected to the interconnect comprising a resistance device setting an output resistance of the write driver substantially equal to the odd characteristic impedance of the interconnect and being selectively activated to generate a voltage pulse to an input of the resistance device with an amplitude equal to an output voltage of the write driver and a duration equal to a predetermined time; and

a voltage boosting device connected between the interconnect and a high voltage reference, the voltage boosting device comprising a pair of current generators connected to the high voltage reference generating the pulsed current, a decoupling device connected between the current generators and the interconnect turning on for a duration equal to the predetermined time, and a capacitance device connected between outputs of the current generators and the decoupling device.

13. The write driver of claim 12, wherein each of the current generators comprises a transistor maintained out of saturation during the operating period.

14. The write driver of claim 12, wherein the decoupling circuit comprises a transistor connected to an output node of the capacitance device and a voltage source coupled to the transistor providing a bias voltage to the transistor, the transistor periodically operating during the operating period allowing the pulsed current to flow from the capacitance device to the write head via the interconnect.

15. The write driver of claim 12, wherein the decoupling circuit further comprises a second transistor connected to the output node of the capacitance device and wherein the pulsed current comprises a positive pulse during which the transistor of the decoupling device delivers the pulsed current to the interconnect and pre-charges the capacitance device and a negative pulse during which the second transistor of the decoupling device delivers the pulsed current to the interconnect and discharges the capacitance device.