Data processing apparatus

• US 20050237825A1
• Filed: 04/27/2005
• Published: 10/27/2005
• Est. Priority Date: 04/27/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Yamazoe, Takanori, Terasawa, Masaaki, Kawajiri, Yoshiki
• Granted Patent: US 7,251,162 B2
• Time in Patent Office: Days
• US Class Current: 365/189.110
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

Claims

1. A semiconductor integrated circuit device comprising:

a memory cell array having a plurality of nonvolatile memory cells; and

a voltage generator for generating a voltage to be supplied to said nonvolatile memory cell,

wherein said voltage generator comprises;

a clock signal controller for generating a first clock signal and a second clock signal having a frequency higher than that of said first clock signal and selecting and outputting one of said first and second clock signals; and

a charge pump circuit for boosting a voltage by pumping operation using either said first clock signal or said second clock signal output from said clock signal controller, thereby generating an operation voltage,

wherein said clock signal controller outputs said first clock signal and then said second clock signal to said charge pump circuit, and

wherein said charge pump circuit generates said operation voltage from a first voltage level to a second voltage level by a voltage boosting operation using said first clock signal output from said clock signal controller, supplies said operation voltage to said nonvolatile memory cell, after that, generates said operation voltage from said second voltage level to a third voltage level by said voltage boosting operation using said second clock signal, and supplies said operation voltage to said nonvolatile memory cell, and

wherein said voltage generator controls so that a first boost ratio of said operation voltage generated by said voltage boosting operation using said first clock signal is lower than a second boost ratio of said operation voltage generated by said voltage boosting operation using said second clock signal.

2. The semiconductor integrated circuit device according to claim 1,

wherein said clock signal controller selects said first clock signal and outputs said first clock signal to said charge pump circuit for a first period of time and, after that, selects said second clock signal and outputs said second clock signal to said charge pump circuit.

3. The semiconductor integrated circuit device according to claim 2,

wherein said clock signal controller comprises:

an oscillator for generating said first clock signal and said second clock signal in response to an oscillation control signal;

a clock selector for outputting either said first clock signal or said second clock signal generated by said oscillator in response to said clock control signal; and

a control circuit for generating a clock control signal which makes said first clock signal output to said clock selector for said first period of time and, after that, makes said second clock signal output.

4. The semiconductor integrated circuit device according to claim 3,

wherein said voltage generator comprises a clock stop detector for detecting that said charge pump circuit outputs a voltage of said third voltage level as said operation voltage and outputting a clock stop signal to stop outputting of said second clock signal from said clock signal controller.

5. The semiconductor integrated circuit device according to claim 4,

wherein said first period of time in which said control circuit outputs said first clock signal is about ⅓

of time required for outputting said operation voltage from said charge pump circuit to reach said third voltage level.

6. The semiconductor integrated circuit device according to claim 1,

wherein said clock signal controller outputs said first clock signal until output of said operation voltage reached at said second voltage level from said charge pump circuit is detected, and outputs said second clock signal until output of said operation voltage reached at said third voltage level from said charge pump circuit is detected.

7. The semiconductor integrated circuit device according to claim 6,

wherein said clock signal controller comprises:

a voltage detector for detecting a voltage level of said operation voltage output from said charge pump circuit and outputting a voltage detection signal according to said voltage level of said operation voltage;

an oscillator for generating said first and second clock signals in accordance with an oscillation control signal; and

a clock selector for selecting and outputting said first clock signal until receiving a first voltage detection signal which is output according to receiving said operation voltage of said second voltage level from said voltage detector and, when said first voltage detection signal is input from said voltage detector, selecting and outputting said second clock signal in place of said first clock signal.

8. The semiconductor integrated circuit device according to claim 7,

wherein said voltage level of said operation voltage detected by said voltage detector is about ⅓

of said third voltage level output from said charge pump circuit.

9. The semiconductor integrated circuit device according to claim 8,

wherein said voltage generator comprises a clock stop detector for outputting a clock stop signal when said voltage level of said operation voltage output from said charge pump circuit becomes said third voltage level, and

wherein said clock signal controller stops outputting of said second clock signal in response to outputting said clock stop signal.