Semiconductor memory device employing clamp for preventing latch up

• US 20050237833A1
• Filed: 12/23/2004
• Published: 10/27/2005
• Est. Priority Date: 04/27/2004
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Byeon, Sang-Jin, Lee, Kang-Seol
• Granted Patent: US 7,417,909 B2
• Time in Patent Office: Days
• US Class Current: 365/203
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A semiconductor memory device employs a clamp for preventing latch up. For the purpose, the semiconductor memory device includes a precharging/equalizing unit for precharging and equalizing a pair of bit lines, and a control signal generating unit for producing a control signal which controls enable and disable of the precharging/equalizing unit, wherein the control signal generating unit includes a clamping unit to clamp its source voltage to a voltage level lower than that of its bulk bias.

Claims

1. A semiconductor memory device comprising:

means for precharging and equalizing a pair of bit lines; and

means for generating a control signal which controls enable and disable of the precharging/equalizing means,

wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias.

2. The semiconductor memory device of claim 1, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.

3. The semiconductor memory device of claim 2, wherein the clamping means has an NMOS transistor whose gate is coupled with the boosted voltage and source is provided with a supply voltage, and which receives the reduced voltage as a bulk bias, and the output voltage of the clamping means is generated through a drain of said NMOS transistor.

4. The semiconductor memory device of claim 1, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the clamping means as its source voltage.

5. The semiconductor memory device of claim 4, wherein the clamping means has a PMOS transistor whose gate is coupled with the reduced voltage and source is provided with a ground voltage, and which receives the boosted voltage as a bulk bias, and the output voltage of the clamping means is produced through a drain of said PMOS transistor.

6. A semiconductor memory device comprising:

a sense amplifier, connected to a pair of bit lines, for amplifying electric potential difference of the bit line pair;

a sense amplifier driver which includes means for precharging and equalizing a driving voltage line of the sense amplifier and drives the sense amplifier driving voltage line; and

a control signal generating means which produces a control signal to control enable and disable of the precharging/equalizing means in the sense amplifier driver, wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias.

7. The semiconductor memory device of claim 6, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.

8. The semiconductor memory device of claim 7, wherein the clamping means has an NMOS transistor whose gate is coupled with the boosted voltage and source is provided with a supply voltage, and which receives the reduced voltage as a bulk bias, and the output voltage of the clamping means is generated through a drain of said NMOS transistor.

9. The semiconductor memory device of claim 6, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the clamping means as its source voltage.

10. The semiconductor memory device of claim 9, wherein the clamping means has a PMOS transistor whose gate is coupled with the reduced voltage and source is provided with a ground voltage, and which receives the boosted voltage as a bulk bias, and the output voltage of the clamping means is produced through a drain of said PMOS transistor.

11. A semiconductor memory device comprising:

a pair of data lines;

means for driving an input signal to the data line pair;

means for precharging and equalizing the data line pair;

a first clamping means for clamping a source voltage of the data line driving means to a voltage level lower than that of a bulk bias of the data line driving means; and

a second clamping means for clamping a source voltage of the precharging/equalizing means to a voltage level lower than that of a bulk bias of the precharging/equalizing means.

12. The semiconductor memory device of claim 11, wherein the driving means includes a PMOS transistor and an NMOS transistor which are connected to the data line pair and whose gates receives a control signal and drains commonly form an output node connected to the data line, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the first clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.

13. The semiconductor memory device of claim 12, wherein the first clamping means has an NMOS transistor whose gate is coupled with the boosted voltage and source is provided with a core voltage, and which receives the reduced voltage as a bulk bias, and the output voltage of the first clamping means is generated through a drain of said NMOS transistor.

14. The semiconductor memory device of claim 11, wherein the precharging/equalizing means PMOS transistors which are connected to the data line pair and whose gates receives a control signal and drains form an output node connected to the data line pair, one PMOS transistor of said PMOS transistors using a boosted voltage as a bulk bias and receiving an output voltage of the second clamping means as its source voltage, and the other PMOS transistor of said PMOS transistors receiving the control signal through its gate and whose source and drain are connected to the data line pair, respectively.

15. The semiconductor memory device of claim 14, wherein the second clamping means has an NMOS transistor whose gate is coupled with the boosted voltage and source is provided with a core voltage, and which receives the reduced voltage as a bulk bias, and the output voltage of the second clamping means is generated through a drain of said NMOS transistor.

16. The semiconductor memory device of claim 11, wherein the driving means includes a PMOS transistor and an NMOS transistor which are connected to the data line pair and whose gates receives a control signal and drains commonly form an output node connected to the data line, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the first clamping means as its source voltage.

17. The semiconductor memory device of claim 16, wherein the first clamping means has a PMOS transistor whose gate is coupled with the reduced voltage and source is provided with a ground voltage, and which receives the boosted voltage as a bulk bias, and the output voltage of the first clamping means is generated through a drain of said PMOS transistor.

18. A semiconductor memory device comprising:

a pair of local data input/output (I/O) lines and a pair of segment data input/output (I/O) lines;

an isolation switching means for controlling transmission between the segment data I/O line pair and the local data I/O line pair;

means for equalizing the segment data I/O line pair and the local data I/O line pair; and

means for generating a control signal used to control enable and disable of the equalizing means,

wherein the control signal generating means includes a clamping means to clamp its source voltage to a voltage level lower than that of its bulk bias.

19. The semiconductor memory device of claim 18, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving an output voltage of the clamping means as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving a ground voltage as its source voltage.

20. The semiconductor memory device of claim 19, wherein the clamping means has an NMOS transistor whose gate is coupled with the boosted voltage and source is provided with a supply voltage, and which receives the reduced voltage as a bulk bias, and the output voltage of the clamping means is generated through a drain of said NMOS transistor.

21. The semiconductor memory device of claim 18, wherein the control signal generating means includes a PMOS transistor and an NMOS transistor whose gates commonly form an input node and drains commonly form an output node of the control signal generating means, the PMOS transistor using a boosted voltage as a bulk bias and receiving a supply voltage as its source voltage, and the NMOS transistor using a reduced voltage as its bulk bias and receiving an output voltage of the clamping means as its source voltage.

22. The semiconductor memory device of claim 21, wherein the clamping means has a PMOS transistor whose gate is coupled with the reduced voltage and source is provided with a ground voltage, and which receives the boosted voltage as a bulk bias, and the output voltage of the clamping means is produced through a drain of said PMOS transistor.