Programmable packet parsing processor

• US 20050238012A1
• Filed: 08/25/2004
• Published: 10/27/2005
• Est. Priority Date: 04/26/2004
• Status: Active Grant

• Current Assignee: Abhijit Patra, Daniel Yu-Kwong Ng, Jackie Liu, Nagaraj A. Bagepalli, Rina Panigrahy, Sanjay Jain
• Original Assignee: Abhijit Patra, Daniel Yu-Kwong Ng, Jackie Liu, Nagaraj A. Bagepalli, Rina Panigrahy, Sanjay Jain
• Inventors: Patra, Abhijit, Jain, Sanjay, Panigrahy, Rina, Bagepalli, Nagaraj A., Ng, Daniel Yu-Kwong, Liu, Jackie
• Granted Patent: US 7,623,468 B2
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 63/0254 Stateful filtering
• CPC Class Codes: H04L 63/1408 by monitoring network traffic monitoring network traffic per se H04L43/00
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

The present invention provides a packet processing device and method. A parsing processor provides instruction-driven content inspection of network packets at 10-Gbps and above with a parsing engine that executes parsing instructions. A flow state unit maintains statefulness of packet flows to allow content inspection across several related network packets. A state-graph unit traces state-graph nodes to keyword indications and/or parsing instructions. The parsing instructions can be derived from a high-level application to emulate user-friendly parsing logic. The parsing processor sends parsed packets to a network processor unit for further processing.

Claims

1. A packet parsing processor, comprising:

a state-graph unit to store parsing instructions for content inspection of network packets at memory locations representative of packet parsing states; and

a parsing engine, having an input/output coupled to an input/output of the state-graph unit to receive the parsing instructions and having an input coupled to receive a network packet, the parsing engine to execute a first parsing instruction located at a current packet parsing state against a byte steam from the network packet to determine a next packet parsing state.

2. The packet processor of claim 1, wherein the current packet parsing state comprises a bit indicating that the current packet parsing state contains the first parsing instruction.

3. The packet processor of claim 1, wherein the parsing engine further comprises a register to store the data, wherein the first parsing instruction comprises a register instruction to perform actions on the data.

4. The packet processor of claim 3, wherein the register instruction copies a current byte from a byte stream across a plurality of related network packets from the network packet to the register.

5. The packet processor of claim 3, wherein the register instruction skips a defined number of bytes within a byte stream spanning across a plurality of related network packets from the network packet to the register.

6. The packet processor of claim 3, wherein the register instruction copies a bit operand to the register.

7. The packet processor of claim 3, wherein the register instruction converts a string representation of a number to a register value.

8. The packet processor of claim 1, wherein the parsing engine further comprises a register, wherein the first parsing instruction comprises a function call instruction to save a current parsing state address in the register and jump to a subroutine.

9. The packet processor of claim 8, further comprising a return instruction to jump back to the current state address stored in the register.

10. The packet processor of claim 1, wherein the first parsing instruction comprises a messaging instruction to send bytes from a byte stream to external to the packet parsing processor for additional processing.

11. The packet processor of claim 1, further comprising a hash table to store portions of parsing states, wherein the first parsing instruction comprises a hash instruction.

12. The packet processor of claim 11, wherein the hash instruction calculates a hash key indicative of an entry in the hash table.

13. The packet processor of claim 11, wherein the hash instruction modifies an entry in the hash table.

14. The packet processor of claim 1, wherein the first parsing instruction comprises a bit vector instruction to perform a logical operation against a bit vector related to a parsing context maintained across a plurality of related network packets.

15. The packet processor of claim 1, wherein the first parsing instruction comprises a location of the next parsing state.

16. The packet processor of claim 1, wherein the byte stream comprises payload data from the network packet.

17. The packet processor of claim 1, wherein the byte stream comprises header data from the network packet.

18. In a packet parsing processor, a method comprising:

storing parsing instructions for content inspection of network packets at memory locations representative of packet parsing states;

receiving a first parsing instruction and a network packet; and

executing a first parsing instruction located at a current packet parsing state against a byte stream of the network packet to determine a next packet parsing state.

19. The method of claim 18, further comprising:

indicating that the current packet parsing state contains the first parsing instruction.

20. The method of claim 18, wherein the first parsing instruction comprises a register instruction to perform actions on the data.

21. The method of claim 20, wherein the register instruction copies a current byte from the byte stream spanning across a plurality of related network packets from a network packet to a register.

22. The method of claim 20, wherein the register instruction skips a defined number of bytes within the byte stream spanning across a plurality of related network packets from the network packet to a register.

23. The method of claim 20, wherein the register instruction copies a bit operand to a register.

24. The method of claim 20, wherein the register instruction converts a string representation of a number to a register value.

25. The method of claim 18, wherein the first parsing instruction comprises a function call instruction to save a current parsing state address in a register and jump to a subroutine.

26. The method of claim 25, further comprising a return instruction to jump back to the current parsing state address stored in the register.

27. The method of claim 18, wherein the first parsing instruction comprises a messaging instruction to send bytes from the byte stream to external to the packet parsing processor for additional processing.

28. The method of claim 18, wherein the first parsing instruction comprises a hash instruction to perform an action related to the hash table.

29. The method of claim 28, wherein the hash instruction calculates a hash key indicative of an entry in the hash table.

30. The method of claim 28, wherein the hash instruction modifies an entry in a hash table.

31. The method of claim 18, wherein the first parsing instruction comprises a bit vector instruction to perform a logical operation against a bit vector related to a parsing context maintained across a plurality of related network packets.

32. The method of claim 18, wherein the first parsing instruction comprises a location of the next packet parsing state.

33. A packet parsing processor, comprising:

means for storing parsing instructions for content inspection of network packets at memory locations representative of packet parsing states;

means for receiving a first parsing instruction and a network packet; and

means for executing, coupled to the means for storing and the means for receiving, the means for executing performing an action on a first parsing instruction located at a current packet parsing state against a byte stream of the network packet to determine a next packet parsing state.

34. The packet parsing processor of claim 33, further comprising:

means for indicating that the first packet parsing state contains the first parsing instruction.

35. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a register instruction to perform actions on the data.

36. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a function call instruction to save a current parsing state address in a register and jump to the next parsing state.

37. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a messaging instruction to send bytes from the byte stream to external to the packet parser for processing.

38. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a hash instruction to perform an action related to a means for hashing.

39. The packet parsing processor of claim 38, wherein the hash instruction calculates a hash key indicative of an entry in the means for hashing.

40. The packet parsing processor of claim 38, wherein the hash instruction modifies an entry in the means for hashing.

41. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a bit vector instruction to perform a logical operation against a bit vector related to a parsing context maintained across a plurality of related network packets.

42. The packet parsing processor of claim 33, wherein the first parsing instruction comprises a location of the next packet parsing state.

43. A computer program product, comprising a computer-readable medium having computer program instructions and data embodied thereon for a method of parsing packets in a packet parsing processor, the method comprising:

storing parsing instructions for content inspection of network packets at memory locations representative of packet parsing states;

receiving a first parsing instruction and a network packet; and

executing a first parsing instruction located at a current packet parsing state against a byte stream of the network packet to determine a next packet parsing state.

44. The computer program product of claim 43, further comprising:

indicating that the first packet parsing state contains the first parsing instruction.

45. The computer program product of claim 43, wherein the first parsing instruction comprises a register instruction to perform actions on the data.

46. The computer program product of claim 43, wherein the first parsing instruction comprises a function call instruction to save a current parsing state address in a register and jump to a subroutine.

47. The computer program product of claim 43, wherein the first parsing instruction comprises a messaging instruction to send bytes from a byte stream to external to the packet parser for processing.

48. The computer program product of claim 43, wherein the first parsing instruction comprises a hash instruction to perform an action related to a hash table.

49. The computer program product of claim 48, wherein the hash instruction calculates a hash key indicative of an entry in the hash table.

50. The computer program product of claim 48, wherein the hash instruction modifies an entry in the hash table.

51. The computer program product of claim 43, wherein the first parsing instruction comprises a bit vector instruction to perform a logical operation against a bit vector related to a parsing context maintained across a plurality of related network packets.

The computer program product of claim 43, wherein the first parsing instruction comprises a location of the next packet parsing state.

52. A network device having a processor and a memory, comprising:

a state-graph unit to store parsing instructions for content inspection of network packets at memory locations representative of packet parsing states; and

a parsing engine, having an input/output coupled to an input/output of the state-graph unit to receive the parsing instructions and having an input coupled to receive a network packet, the parsing engine to execute a first parsing instruction located at a current packet parsing state against a byte steam from the network packet to determine a next packet parsing state.