Byte-configurable memory in an optical transceiver

• US 20050238359A1
• Filed: 03/07/2005
• Published: 10/27/2005
• Est. Priority Date: 03/05/2004
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Finisar Corporation (II-VI Incorporated)
• Inventors: Hahin, Jayne C., Dybsetter, Gerald L.
• Granted Patent: US 8,090,265 B2
• Time in Patent Office: Days
• US Class Current: 398/135
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G06F 12/1483 using an access-table, e.g. matrix or list
• CPC Class Codes: G06F 12/1491 in a hierarchical protection system, e.g. privilege levels, memory rings

Abstract

A mechanism that enables an optical transceiver to configure memory on a per-segment basis. The optical transceiver includes a processing entity, system memory and a memory configuration table. The memory configuration table is comprised of configuration entries, each of which defines the configuration setting for a corresponding segment of memory. The processing entity reads the configuration entries for a particular segment of the memory. The processing entity then determines the set of one or more configuration settings for the memory segment based on the configuration entry read. This process may be repeated for multiple segments of memory.

Claims

1. In an optical transceiver including a processing entity, a system memory, and a memory configuration table having a plurality of configuration entries, each configuration entry for defining at least one configuration setting for a corresponding memory segment, a method for configuring the system memory on a per-segment basis, the method comprising:

an act of the processing entity reading a first configuration entry defining a first set of one or more configuration settings for a first memory segment;

an act of the processing entity determining configuration settings for the first memory segment based on the first configuration entry read;

an act of the processing entity reading a second configuration entry defining a second set of one or more configuration settings for a second memory segment; and

an act of the processing entity determining configuration settings for the second memory segment based on the second configuration entry read.

2. A method in accordance with claim 1, wherein the memory configuration table comprises a plurality of hierarchical configuration tables.

3. A method in accordance with claim 2, wherein the plurality of hierarchical configuration tables include one or more lower-level configuration tables.

4. A method in accordance with claim 3, wherein one or more of the plurality of hierarchical configuration tables include indexes indexing into one or more lower-level configuration tables.

5. A method in accordance with claim 1, wherein at least one of the first set of one or more configuration settings defines whether or not the first memory segment is writeable.

6. A method in accordance with claim 1, wherein at least one of the first set of one or more configuration settings defines whether or not the first memory segment is readable.

7. A method in accordance with claim 1, wherein at least one of the first set of one or more configuration settings defines whether or not a write to the first memory segment should trigger a processor interrupt.

8. A method in accordance with claim 1, wherein at least one of the first set of one or more configuration settings defines whether or not the first memory segment is non-volatile memory.

9. A method in accordance with claim 1, wherein at least one of the first set of one or more configuration settings defines whether or not the first memory segment is volatile memory.

10. A method in accordance with claim 1, wherein a second memory segment is a power of two times smaller than a first memory segment.

11. A method in accordance with claim 10, wherein a third memory segment is a power of two times smaller than the second memory segment.

12. A method in accordance with claim 11, wherein a fourth memory segment is a power of two times smaller than the third memory segment.

13. A method in accordance with claim 1, wherein the processing entity is a state machine.

14. A method in accordance with claim 1, wherein the processing entity is a processor.

15. A method in accordance with claim 1, wherein the memory configuration table contains configuration settings for at least two separate devices.

16. An optical transceiver comprising:

a processing entity;

a system memory;

a memory configuration table having a plurality of configuration entries, each configuration entry for defining at least one configuration setting for a corresponding memory segment;

wherein configuring the system memory on a per-segment basis comprises;

the processing entity reading a first configuration entry defining a first set of one or more configuration settings for a first memory segment;

the processing entity determining configuration settings for the first memory segment based on the first configuration entry read;

the processing entity reading a second configuration entry defining a second set of one or more configuration settings for a second memory segment; and

the processing entity determining configuration settings for the second memory segment based on the second configuration entry read.

17. An optical transceiver in accordance with claim 16, wherein the memory configuration table comprises a plurality of hierarchical configuration tables.

18. An optical transceiver in accordance with claim 17, wherein the plurality of hierarchical configuration tables include one or more low-level configuration tables.

19. An optical transceiver in accordance with claim 18, wherein one or more of the plurality of hierarchical configuration tables include indexes indexing into one or more low-level configuration tables.

20. An optical transceiver in accordance with claim 16, wherein the processing entity is one of a state machine or a processor.