Integrated circuit structure with improved LDMOS design

• US 20050239253A1
• Filed: 03/01/2005
• Published: 10/27/2005
• Est. Priority Date: 12/10/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: CAI Jun
• Inventors: Cai, Jun
• Granted Patent: US 7,220,646 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor integrated circuit including an LDMOS device structure comprises a semiconductor layer with a pair of spaced-apart field effect gate structures over an upper surface of the semiconductor layer. First and second spaced-apart source regions of a first conductivity type are formed in a portion of the layer between the pair of gate structures with a first region of a second conductivity type formed there between. A lightly doped body region of a second conductivity type is formed in the semiconductor layer, extending from below the source regions to below the gate structures and extending a variable depth into the semiconductor layer. This body region is characterized by an inflection in depth in that portion of the body region extending below the first region.

Claims

1. A method of forming a semiconductor device comprising:

providing a layer of semiconductor material;

forming with a first mask level a pair of spaced-apart field effect gate structures on a surface of a semiconductor layer, each structure including a first end portion facing the other gate structure;

forming with a second mask level first and second spaced-apart source regions of a first conductivity type in the layer and between the pair of gate structures with a resulting region of the surface between the first and second spaced-apart source regions having a first area dimension;

also forming with the second mask level a lightly doped body region of a second conductivity type in the layer and extending below the source regions; and

forming a more heavily doped region of the second conductivity type in a portion of the semiconductor layer having a surface with the first area dimension, said portion having a surface with an area dimension smaller than the first area dimension.

2. The method of claim 1 wherein the source regions are formed with a single implantation step of the first conductivity type.

3. The method of claim 1 wherein each source region is formed in self-alignment with a different gate structure end portion.

4. The method of claim 3 wherein the source regions are formed in spaced-apart relation to one another by the positioning of a mask layer element over the portion of the surface of the semiconductor layer between the pair of source regions.

5. The method of claim 1 wherein the source regions each extend beneath a gate structure end portion.

6. The method of claim 1 further including forming a sidewall spacer against a first end portion and over the source region prior to forming the more heavily doped region so that the more heavily doped region is formed in self-alignment with respect to said first end portion.

7. The method of claim 1 further including the step of forming, prior to forming the more heavily doped region, a sidewall spacer over each source region and against one of the first end portions.