Compliant multi-composition interconnects

• US 20050239275A1
• Filed: 04/26/2004
• Published: 10/27/2005
• Est. Priority Date: 04/26/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Muthukumar, Sriram, Dory, Thomas S.
• Granted Patent: US 7,400,041 B2
• Time in Patent Office: Days
• US Class Current: 438/611
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05681 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/13 : of an individual bump connector
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0104 : Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A compliant interconnect with two or more layers of metal of two or more compositions with internal stresses is described herein.

Claims

1. A compliant interconnect comprising:

a first metal layer of a first metal composition having a first thickness and a first amount of internal stress; and

;

a second metal layer of a second metal composition, stacked on top of the first metal layer, the second metal layer having a second thickness and a second amount of internal stress.

2. The compliant interconnect of claim 1, wherein at least a selected one of the first and second metal composition comprises a selected one of (Al, Cu, Ti, Ni, Au, Ag, Sn, Ta, Mo, Cr and Co).

3. The compliant interconnect of claim 1, wherein at least a selected one of the first and second internal stresses is compressive stress.

4. The compliant interconnect of claim 1, wherein at least a selected one of the first and second internal stresses is tensile stress.

5. An apparatus comprising:

a substrate including a metal pad;

a passivation layer disposed on said substrate, including an opening exposing the metal pad; and

a compliant interconnect disposed on a portion of said substrate and said metal pad, the compliant interconnect having at least a first metal layer of a first metal composition with a first thickness and having a first amount of internal stress, and a second metal layer of a second metal composition, stacked on top of the first layer, with a second thickness and having a second amount of internal stress.

6. The apparatus of claim 5, wherein at least a selected one of the first and second metal composition of the compliant interconnect comprises a selected one of (Al, Cu, Ti, Ni, Au, Ag, Sn, Ta, Mo, Cr and Co).

7. The apparatus of claim 5, wherein at least a selected one of the first and second internal stresses of the first and second metal layers of the compliant interconnect is compressive stress.

8. The apparatus of claim 5, wherein at least a selected one of the first and second internal stresses of the first and second metal layers of the compliant interconnect is tensile stress.

9. The apparatus of claim 5, wherein the apparatus is a microprocessor.

10. A system comprising:

a component having;

a substrate including a metal pad;

a passivation layer disposed on the substrate, including an opening exposing the metal pad;

a compliant interconnect disposed on a portion of the or passivation layer and the metal pad, the compliant interconnect having at least a first metal layer of a first metal composition with a first thickness and having a first amount of internal stress, and a second metal layer of a second metal composition, stacked on top of the first layer, with a second thickness and having a second amount of internal stress;

a bus coupled to the component; and

a networking interface coupled to the bus.

11. The system of claim 10, wherein the component is a selected one of a microprocessor and a chipset.

12. The system of claim 10, wherein at least a selected one of the first and second metal composition of the compliant interconnect of the component comprises a selected one of (Al, Cu, Ti, Ni, Au, Ag, Sn, Ta, Mo, Cr and Co).

13. The system of claim 10, wherein at least a selected one of the first and second internal stresses of the first and second metal layers of the compliant interconnect of the component is compressive stress.

14. The system of claim 10, wherein at least a selected one of the first and second internal stresses of the first and second metal layers of the compliant interconnect of the component is tensile stress.

15. The system of claim 10, wherein said system is selected from the group comprising of a mobile phone, a DVD player, a digital camera, and a set-top box.

16. A method comprising:

forming a substrate with a metal pad;

forming a passivation layer with an opening on top of the substrate, the opening exposing said metal pad; and

forming a compliant interconnect on a portion of the passivation layer and the metal pad, with the compliant interconnect having at least a first metal layer of a first metal composition with a first thickness and having a first amount of internal stress, and a second metal layer of a second metal composition, stacked on top of the first layer, with a second thickness and having a second amount of internal stress.

17. The method of claim 16, wherein the method further comprises forming a polymer dome on top of said dielectric layer at one side of said opening prior to said forming of a compliant interconnect, and said forming of the compliant interconnect comprises forming the compliant interconnect on top of said polymer dome, said pad, and dielectric layer at the other side of the opening.

18. The method of claim 17, wherein the method further comprises removing the polymer dome, after forming at least one metal layer of said compliant interconnect.

19. The method of claim 16, wherein said forming of the compliant interconnect comprises forming at least a selected one of said first and second metal layers via electroplating, where said electroplating is performed in a manner providing the corresponding one of the first and second amount of internal stresses.

20. The method of claim 16, wherein said forming of the compliant interconnect comprises forming at least a selected one of said first and second metal layers via sputtering, where said sputtering is performed in a manner providing the corresponding one of the first and second amount of internal stresses.