Method for forming self-aligned contact in semiconductor device

• US 20050239282A1
• Filed: 09/15/2004
• Published: 10/27/2005
• Est. Priority Date: 04/23/2004
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Lin, Shian-Jyh, Chen, Meng-Hung, Yu, Chia-Sheng
• Granted Patent: US 7,094,672 B2
• Time in Patent Office: Days
• US Class Current: 438/629
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of forming a first insulating layer comprising a nitride along a profile of a gate structure and a junction region, forming a temporary layer comprising a doped oxide on the first insulating layer, removing a portion of the temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of the temporary layer over the junction region, forming a second insulating layer comprising an undoped oxide in a region where the portion of the temporary layer is removed, removing the plug portion by performing a selective etch of the undoped oxide to form a contact hole, removing a portion of the first insulating layer at a bottom of the contact hole, and forming a conductive contact in the contact hole.

Claims

1. A method for forming a self-aligned contact in a semiconductor device, comprising the steps of:

(a) providing a substrate having at least one gate structure and at least one junction region adjacent said gate structure;

(b) forming a first insulating layer along a profile of said gate structure and said junction region;

(c) forming a temporary layer on said first insulating layer;

(d) selectively removing a portion of said temporary layer while leaving a plug portion of said temporary layer over said junction region;

(e) forming a second insulating layer in a region where said portion of said temporary layer is removed;

(f) removing said plug portion to form a contact hole;

(g) removing a portion of said first insulating layer at a bottom of said contact hole; and

(h) forming a conductive contact in said contact hole;

wherein a third insulating layer is formed on side walls of said plug portion after said step

3. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said first insulating layer is made of silicon nitride (SiN).

4. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said temporary layer is made of borophosphosilicate glass (BPSG).

5. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said temporary layer has a width in a range of 2500˜

3000 Å

.

6. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said step (d) comprises the steps of:

forming a mask having a predetermined pattern on said temporary layer; and

removing a portion of said temporary layer not covered by said mask by using a selective etch process where an etch rate of said temporary layer is higher than an etch rate of said first insulating layer while leaving a plug portion of said temporary layer over said junction region.

7. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said third insulating layer is made of silicon nitride (SiN).

8. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said second insulating layer is made of undoped silicon dioxide (SiO₂).

9. The method for forming a self-aligned contact in a semiconductor device of claim 1, wherein said step (f) comprises the step of:

removing said plug portion by using a selective etch process where an etch rate of said temporary layer is higher than both an etch rate of said first insulating layer and an etch rate of said second insulating layer to form a contact hole.

10. The method for forming a self-aligned contact in a semiconductor device of claim 9, wherein said selective etch process is performed by using an etchant comprising vapor hydrofluoric acid (Vapor HF).

2. (canceled)

11. A method for forming a self-aligned contact in a semiconductor device, comprising the steps of:

(a) providing a substrate having at least one gate structure and at least one junction region adjacent said gate structure;

(b) forming a first insulating layer comprising a nitride along a profile of said gate structure and said junction region;

(c) forming a temporary layer comprising a doped oxide on said first insulating layer;

(d) removing a portion of said temporary layer by performing a selective etch of the oxide with a mask while leaving a plug portion of said temporary layer over said junction region;

(e) forming a second insulating layer comprising an undoped oxide in a region where said portion of said temporary layer is removed;

(f) removing said plug portion by performing a selective etch of the doped oxide to form a contact hole;

(g) removing a portion of said first insulating layer at a bottom of said contact hole; and

(h) forming a conductive contact in said contact hole.

12. The method for forming a self-aligned contact in a semiconductor device of claim 11, further comprising forming a third insulating layer on side walls of said plug portion after said step (d).

13. The method for forming a self-aligned contact in a semiconductor device of claim 11, where in said first insulating layer comprises silicon nitride (SiN).

14. The method for forming a self-aligned contact in a semiconductor device of claim 11, wherein said temporary layer comprises borophosphosilicate glass (BPSG).

15. The method for forming a self-aligned contact in a semiconductor device of claim 11, wherein said temporary layer has a width in a range of 2500˜

3000 Å

.

16. The method for forming a self-aligned contact in a semiconductor device of claim 11, wherein said step (d) comprises the steps of:

forming a mask having a predetermined pattern on said temporary layer; and

removing a portion of said temporary layer not covered by said mask by using a selective etch process where an etch rate of the oxide is higher than an etch rate of the nitride while leaving a plug portion of said temporary layer over said junction region.

17. The method for forming a self-aligned contact in a semiconductor device of claim 12, wherein said third insulating layer comprises silicon nitride (SiN).

18. The method for forming a self-aligned contact in a semiconductor device of claim 11, wherein said second insulating layer comprises undoped silicon dioxide (SiO₂).

19. The method for forming a self-aligned contact in a semiconductor device of claim 11, wherein said step (f) comprises the step of:

removing said plug portion by using a selective etch process where an etch rate of the doped oxide is higher than both an etch rate of the undoped oxide and an etch rate of the nitride to form a contact hole.

20. The method for forming a self-aligned contact in a semiconductor device of claim 19, wherein said selective etch process is performed by using an etchant comprising vapor hydrofluoric acid (Vapor HF).