High-frequency switch circuit and high-frequency transmitting/receiving apparatus

• US 20050239415A1
• Filed: 07/06/2004
• Published: 10/27/2005
• Est. Priority Date: 04/27/2004
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Seshita, Toshiki, Sagae, Yoshitomo
• Application Number:
  US10/883,697
• Publication Number:
  US 20050239415A1
• Time in Patent Office: Days
• US Class Current: 455/78
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A high-frequency switch circuit includes a first terminal which receives a transmission signal, a first FET which makes a path of the transmission signal conductive or cut off, a second terminal which receives a control signal that is inactive in a transmitting mode and is active in a receiving mode, a ground terminal which is grounded via a first capacitor, and a second FET which has a drain electrode, a source electrode and a gate electrode, the drain or source electrode being connected to the ground terminal, the source or drain electrode being connected to first terminal, and the gate electrode being connected to the second terminal, and which has a greater off-capacitance for unit gate width than the first FET.

Claims

1. A high-frequency switch circuit which switches between a transmitting mode of inputting and outputting a transmission signal and a receiving mode of inputting and outputting a reception signal, said circuit comprising:

a first terminal which receives the transmission signal;

a first FET (field-effect transistor) which makes a path of the transmission signal conductive or cut off;

a second terminal which receives a control signal that is inactive in the transmitting mode and is active in the receiving mode;

a ground terminal which is grounded via a first capacitor; and

a second FET which has a drain electrode, a source electrode and a gate electrode, the drain or source electrode being connected to the ground terminal, the source or drain electrode being connected to first terminal, and the gate electrode being connected to the second terminal, and which has a greater off-capacitance for unit gate width than the first FET.

2. The switch circuit according to claim 1, wherein the gate electrode of the second FET is formed on a semiconductor substrate, is T-shaped and has two overhangs.

3. The switch circuit according to claim 2, wherein a gate electrode of the first FET has two overhangs, and the overhangs of the second FET lie at a level higher than those of the first FET, from a surface of the semiconductor substrate.

4. The switch circuit according to claim 2, wherein a gate electrode of the first FET has two overhangs, and the overhangs of the second FET are longer than those of the first FET.

5. The switch circuit according to claim 2, further comprising a first insulating film provided between the semiconductor substrate and the overhangs of the second FET.

6. The switch circuit according to claim 1, further comprising a first wiring portion connecting a first node to the first terminal, wherein,

the drain or source electrode of the first FET is connected to the first terminal by the first node;

the second FET is connected to the first terminal by the first node; and

the second FET has an off-capacitance and the first wiring portion has inductance, said off-capacitance and said inductance performing impedance matching on a high-frequency power amplifier connected to the first terminal.

7. The switch circuit according to claim 6, wherein the off-capacitance of the second FET changes an output impedance of the high-frequency power amplifier to a predetermined value.

8. The switch circuit according to claim 6, which is sealed in a package substrate and in which the first wiring portion includes a bonding wire.

9. The switch circuit according to claim 8, wherein the first wiring portion includes a lead which electrically connected to an external terminal.

10. The switch circuit according to claim 1, which is provided on a dielectric substrate having a high-frequency power amplifier, which further comprises a second wiring portion connecting an output of the high-frequency power amplifier to the first terminal, and in which the second FET has an off-capacitance and the second wiring portion has inductance, said off-capacitance and said inductance performing impedance matching on the high-frequency power amplifier.

11. The switch circuit according to claim 10, wherein the second wiring portion includes a bonding wire.

12. The switch circuit according to claim 1, further comprising:

a second insulating film which is provided on the gate electrode of the second FET; and

a first conductive layer which has an overhang connected to the drain source of the second FET and provided on the second insulating film.

13. The switch circuit according to claim 1, further comprising:

a third insulating film which is provided on the gate electrode of the second FET; and

a second conductive layer which has an overhang connected to the source electrode of the second FET and provided on the third insulating film.

14. The switch circuit according to claim 1, wherein;

the second FET is a multi-gate FET having first and second gate electrodes, which are T-shaped and have two overhangs each;

the second gate electrode is arranged below one of the overhangs of the first gate electrode; and

a fourth insulating film is interposed between the second gate electrode and said one of the overhangs.

15. The switch circuit according to claim 1, wherein;

the second FET is a multi-gate FET having first, second and third gate electrodes, which are T-shaped and have two overhangs each;

the second gate electrode is arranged below one of the overhangs of the first gate electrode;

a fourth insulating film is interposed between the second gate electrode and said one of the overhangs of the first gate electrode;

the third gate electrode is arranged below the other of the overhangs of the first gate electrode; and

a fifth insulating film interposed between the third gate electrode and said other of the overhangs of the first gate electrode.

16. The switch circuit according to claim 1, wherein each of the FETs is a MESFET (metal-semiconductor field-effect transistor) or a HEMT (high electron mobility transistor).

17. A high-frequency transmitting/receiving apparatus comprising:

a dielectric substrate;

a high-frequency power amplifier which is provided on the dielectric substrate and which amplifies a transmission signal;

an inductor connected at one end to a power-supply voltage and at the other end connected to an output of the high-frequency power amplifier; and

a high-frequency switch circuit which is provided on the dielectric substrate, which is sealed in a package substrate and which switches between a transmitting mode of inputting and outputting the transmission signal and a receiving mode of inputting and outputting a reception signal, said switch circuit comprising;

a first terminal which receives the transmission signal;

a wiring portion which connects a first node to the first terminal;

a first FET which has a drain electrode, a source electrode and a gate electrode, the drain or source electrode being connected to the first node, and which makes a path of the transmission signal conductive or cut off;

a second terminal which receives a control signal that is inactive in the transmitting mode and is active in the receiving mode;

a ground terminal which is grounded via a first capacitor; and

a second FET which has a drain electrode, a source electrode and a gate electrode, the drain or source electrode being connected to the first node, the source or drain electrode being connected to the ground terminal, and the gate electrode being connected to the second terminal, and which has a greater off-capacitance for unit gate width than the first FET,

the second FET having an off-capacitance, and the wiring portion having inductance, said off-capacitance and said inductance performing impedance matching on the high-frequency power amplifier.

18. The transmitting/receiving apparatus according to claim 17, wherein the off-capacitance of the second FET changes an output impedance of the high-frequency power amplifier to a predetermined value.

19. The transmitting/receiving apparatus according to claim 17, wherein the gate electrode of the second FET is T-shaped and has two overhangs.

20. A high-frequency transmitting/receiving apparatus comprising:

a dielectric substrate;

a high-frequency power amplifier which is provided on the dielectric substrate and which amplifies a transmission signal;

an inductor connected at one end to a power-supply voltage and at the other end connected to an output of the high-frequency power amplifier; and

a high-frequency switch circuit which is provided on the dielectric substrate and which switches between a transmitting mode of inputting and outputting the transmission signal and a receiving mode of inputting and outputting a reception signal, said switch circuit comprising;

a first terminal which receives the transmission signal;

a first FET which makes a path of the transmission signal conductive or cut off;

a second terminal which receives a control signal that is inactive in the transmitting mode and is active in the receiving mode;

a ground terminal which is grounded via a first capacitor;

a second FET which has a drain electrode, a source electrode and a gate electrode, the drain or source electrode being connected to the first terminal, the source or drain electrode being connected to the ground terminal, and the gate electrode being connected to the second terminal, and which has a greater off-capacitance for unit gate width than the first FET, and

a wiring portion which connects the first terminal to the output of the high-frequency power amplifier,

the second FET having an off-capacitance, and the wiring portion having inductance, said off-capacitance and said inductance performing impedance matching on the high-frequency power amplifier.