High speed memory control and I/O processor system

• US 20050240745A1
• Filed: 12/17/2004
• Published: 10/27/2005
• Est. Priority Date: 12/18/2003
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Iyer, Sundar, McKeown, Nick
• Granted Patent: US 7,657,706 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory

Abstract

An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

Claims

1. A method of improving performance for a computer processor, said method comprising:

reducing memory accesses normally performed by a processor by offloading tasks to an input/output processor;

dividing memory storage tasks performed by said input/output processor into high frequency memory components and low frequency memory components;

storing said high frequency memory components in a high-speed memory; and

storing said low frequency memory components in a slow-speed memory.

2. The method as claimed in claim 1 wherein said high-speed memory comprises static random access memory (SRAM).

3. The method as claimed in claim 1 wherein said slow-speed memory comprises dynamic random access memory (DRAM).

4. The method as claimed in claim 1 wherein said low frequency memory components comprise elements in a FIFO queue wherein said elements are not proximate to a head of said FIFO queue and said elements are not proximate to a tail of said FIFO queue.

5. The method as claimed in claim 1 wherein said high frequency memory components comprise elements in a FIFO queue proximate to a head of said FIFO queue.

6. The method as claimed in claim 1 wherein said high frequency memory components comprise elements in a FIFO queue proximate to a tail of said FIFO queue.

7. The method as claimed in claim 1 wherein said low frequency memory components comprise periodically adjusted full-size counter values.

8. The method as claimed in claim 1 wherein said high frequency memory components comprise recent counter adjustments.

9. The method as claimed in claim 1 wherein said low frequency memory components comprise a look-up table.

10. The method as claimed in claim 1 wherein said high frequency memory components comprise updates to a look-up table.

11. An input/output processor, said input/output processor interfacing a main processor with a slow-speed memory, said input/output processor comprising:

a high-speed memory;

a counter management module, said counter management module for handling at least one statistics counter, said counter management module storing recent counter updates for said statistics counter in said high-speed memory and storing periodically updated counter values in said main memory; and

a FIFO management module, said FIFO management module for managing at least one FIFO queue.

12. The method as claimed in claim 11 wherein said high-speed memory comprises static random access memory (SRAM).

13. The method as claimed in claim 11 wherein said slow-speed memory comprises dynamic random access memory (DRAM).

14. The apparatus as claimed in claim 11, said apparatus further comprising:

a memory management module, said memory management module for maintaining linked lists.

15. The apparatus as claimed in claim 11, said apparatus further comprising:

a netflow management module, said memory management module for performing netflow packet capture.

16. The apparatus as claimed in claim 11, said apparatus further comprising:

a packet scheduling module, said packet scheduling module for performing packet.

17. An apparatus for improving performance for a processor, said apparatus situated between said processor and a slow-speed memory system, said apparatus comprising:

a high-speed memory system; and

a memory access pattern aware controller, said reducing memory accesses normally performed said processor, said memory access pattern aware controller dividing memory access tasks requested by processor into high frequency memory components and low frequency memory components, said memory access pattern aware controller storing said high frequency memory components in said high-speed memory, said memory access pattern aware controller storing said low frequency memory components in said slow-speed memory.

18. The apparatus as claimed in claim 17 wherein said high-speed memory comprises static random access memory (SRAM).

19. The apparatus as claimed in claim 17 wherein said slow-speed memory comprises dynamic random access memory (DRAM).

20. The apparatus as claimed in claim 17 wherein said low frequency memory components comprise elements in a FIFO queue wherein said elements are not proximate to a head of said FIFO queue and said elements are not proximate to a tail of said FIFO queue.

21. The method as claimed in claim 17 wherein said high frequency memory components comprise elements in a FIFO queue proximate to a head of said FIFO queue.

22. The method as claimed in claim 17 wherein said high frequency memory components comprise elements in a FIFO queue proximate to a tail of said FIFO queue.

23. The method as claimed in claim 17 wherein said low frequency memory components comprise periodically adjusted full-size counter values.

24. The method as claimed in claim 17 wherein said high frequency memory components comprise recent counter adjustments.

25. The method as claimed in claim 17 wherein said low frequency memory components comprise a look-up table.

26. The method as claimed in claim 17 wherein said high frequency memory components comprise updates to a look-up table.

27. A method of improving performance for a computer processor, said method comprising:

dividing a set of tasks normally performed by a processor into a compute-intensive portion and an input/output-intensive portion;

performing said compute-intensive portion with said computer processor; and

performing said input/output-intensive portion with an input/output processor coupled to said computer processor wherein said input/output processor comprises control logic, a high-speed memory, and an interface to a slow-speed off-chip memory.

28. The method as claimed in claim 27 wherein said high-speed memory comprises on-chip static random access memory (SRAM).

29. The method as claimed in claim 27 wherein said slow-speed memory comprises off-chip dynamic random access memory (DRAM).