Vertical structure semiconductor devices

• US 20050242365A1
• Filed: 04/27/2005
• Published: 11/03/2005
• Est. Priority Date: 04/28/2004
• Status: Active Grant

• Current Assignee: Verticle, Inc.
• Original Assignee: Verticle, Inc.
• Inventors: Yoo, Myung Cheol
• Granted Patent: US 7,465,592 B2
• Time in Patent Office: Days
• US Class Current: 257/103
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85181 connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

The invention provides a reliable way to fabricate a new vertical structure compound semiconductor device with improved light output and a laser lift-off processes for mass production of GaN-based compound semiconductor devices. A theme of the invention is employing direct metal support substrate deposition prior to the LLO by an electro-plating method to form an n-side top vertical structure. In addition, an ITO DBR layer is employed right next to a p-contact layer to enhance the light output by higher reflectivity. A perforated metal wafer carrier is also used for wafer bonding for easy handling and de-bonding. A new fabrication process is more reliable compared to the conventional LLO-based vertical device fabrication. Light output of the new vertical device having n-side up structure is increased 2 or 3 times higher than that of the lateral device fabricated with same GaN/InGaN epitaxial films.

Claims

1. A method of fabricating semiconductor devices, comprising the steps of:

forming a plurality of semiconductor layers over a substrate;

forming a plurality of metal layers over the semiconductor layers;

removing the substrate from the semiconductor layers;

forming one or more electrical contacts over the semiconductor layers where the substrate was removed; and

separating the semiconductor layers into a plurality of individual semiconductor devices.

2. The method of claim 1, further comprising the step of:

forming a buffer layer between the semiconductor layer and substrate.

3. The method of claim 1, wherein:

the removing step includes the step of applying a laser beam to an interface between the semiconductor layer and substrate, and inserting a diffusing media between the laser source and the substrate for uniform laser beam energy distribution.

4. The method of claim 1, further comprising the step of:

attaching a wafer carrier to the metal layer.

5. The method of claim 2, further comprising the step of:

attaching a wafer carrier to the metal layer.

6. The method of claim 3, further comprising the step of:

attaching a wafer carrier to the metal layer.

7. The method of claim 2, wherein:

the separating step includes the step of forming a trench between each of the respective devices, passivating exposed portions of the devices, and transferring the individual semiconductor devices to a support film.

8. The method of claim 2, further comprising the step of:

assembling the individual semiconductor devices to a lead frame using a one-step die bonding and wire bonding technique.

9. The method of claim 7, further comprising the step of:

assembling the individual semiconductor devices to a lead frame using a one-step die bonding and wire bonding technique.

10. A semiconductor device manufactured according to the method of claim 1.

11. A method of fabricating a light emitting semiconductor device, comprising the steps of:

forming a diode structure over a substrate;

forming a plurality of metal layers over the diode structure;

removing the substrate from the diode structure;

forming one or more contacts over the diode structure where the substrate was removed; and

separating the diode structure into a plurality of individual diodes.

12. The method of claim 11, wherein the step of forming the diode structure comprises the steps of:

depositing a first buffer layer including one of GaN and AlN over the substrate; and

depositing a n-GaN layer over the buffer layer.

13. The method of claim 11, wherein the step of forming the diode structure comprises the steps of:

depositing a first buffer layer including one of GaN and AlN over the substrate;

depositing a second buffer layer including AlGaN over the substrate; and

depositing a n-GaN layer over the buffer layer.

14. The method of claim 12, wherein:

the removing step includes the step of applying a laser beam to an interface between the semiconductor layer and substrate, inserting a diffusing media between the laser source and the substrate, and liquefying at least a portion of the buffer layer.

15. The method of claim 11, wherein:

the separating step includes the step of forming a trench between each of the respective devices, passivating exposed portions of the devices, and transferring the individual semiconductor devices to a support film.

16. The method of claim 11, further comprising the step of:

attaching a wafer carrier to the metal layer.

17. The method of claim 14, further comprising the step of:

attaching a wafer carrier to the metal layer.

18. A semiconductor device manufactured according to the method of claim 11.

19. A semiconductor structure, comprising:

a first buffer layer includes at least one of GaN and AlN;

a second buffer layer including AlGaN;

a layer including n-GaN;

a layer including AlInGaN; and

a layer including p-GaN.

20. The semiconductor structure of claim 19, further comprising:

a substrate.

21. The semiconductor structure of claim 19, further comprising:

a layer including p-AlGaN.

22. The semiconductor structure of claim 19, further comprising:

a metal layer including Cu; and

a metal layer including Au.

24. The semiconductor structure of claim 22, further comprising:

a wafer carrier coupled to the semiconductor structure.

25. The semiconductor structure of claim 22, further comprising:

a layer including n-ITO.

26. The semiconductor structure of claim 25, further comprising:

a plurality of contacts.

27. The semiconductor structure of claim 26, further comprising:

a plurality of trenches disposed between individual semiconductor devices.

28. The semiconductor structure of claim 27, further comprising:

a passivation layer over exposed portions of the devices.

23. The semiconductor structure of claim 23, further comprising:

a wafer carrier coupled to the semiconductor structure.