Semiconductor device and method of making the same

• US 20050242376A1
• Filed: 04/29/2004
• Published: 11/03/2005
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsu, Ju-Wang, Chen, Shih-Chang, Chen, Chien-Hao, Chen, Chia-Lin, Lee, Tze Liang
• Granted Patent: US 7,259,050 B2
• Time in Patent Office: Days
• US Class Current: 257/214
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A semiconductor device comprises a substrate, a gate disposed on the substrate, and a source and drain formed in the substrate on both sides of the gate. The device further comprises a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å per minute using the same etchant.

Claims

1. A method of forming a semiconductor device, comprising:

forming a gate on a semiconductor substrate;

forming a first spacer layer;

forming shallow lightly-doped regions on both sides of the gate in the substrate and being offset from the gate by the first spacer layer;

forming a second spacer layer over the first spacer layer;

etching the first and second spacer layers to form a thick spacer;

forming source and drain regions on both sides of the gate in the substrate and being offset from the gate by the thick spacer; and

etching the thick spacer to form a thin spacer.

2. The method, as set forth in claim 1, wherein etching the thick spacer comprises etching the thick spacer using hydrofluoric acid.

3. The method, as set forth in claim 1, wherein forming a second spacer layer comprises selecting processing parameters to form a second spacer layer having a high hydrofluoric acid etch rate.

4. The method, as set forth in claim 1, wherein forming a second spacer layer comprises selecting processing parameters to form a second spacer layer having an etch rate comparable to the etch rate of the first spacer layer using the same etchant.

5. The method, as set forth in claim 1, wherein forming a second spacer layer comprises depositing a silicon nitride layer at a temperature less than 630°

C. with high hydrofluoric acid etch rate of at least 10 Å

per minute.

6. The method, as set forth in claim 1, wherein forming a first and second spacer layers comprise forming a first spacer layer having silicon oxide and forming a second spacer layer containing nitrogen.

7. The method, as set forth in claim 1, wherein etching the first and second spacer layers to form a thick spacer comprises dry etching the first and second spacer layers.

8. The method, as set forth in claim 1, wherein etching the thick spacer comprises wet etching the thick spacer using hydrofluoric acid.

9. The method, as set forth in claim 1, further comprising annealing the source and drain regions and thereby shrinking the second spacer layer.

10. The method, as set forth in claim 1, further comprising annealing the source and drain regions and thereby shrinking the thick spacer.

11. The method, as set forth in claim 1, further comprising forming a contact etch stop layer over the substrate.

12. The method, as set forth in claim 1, wherein forming the second spacer layer comprises using a precursor selected from the group consisting of HCD, BTBAS, DCS, DS, SiH₄, NH₃, C₂H₄, and N₂.

13. A semiconductor device, comprising:

a substrate;

a gate disposed on the substrate;

a source and drain formed in the substrate on both sides of the gate; and

a thin spacer having a liner layer and a nitrogen-containing layer formed on the sidewalls of the gate, wherein the liner layer and the nitrogen-containing layer have comparable hydrofluoric acid etch rates.

14. The semiconductor device, as set forth in claim 13, wherein the nitrogen-containing layer comprises dopants selected from the group consisting of carbon, oxygen, fluorine, arsenic, boron, and chlorine.

15. The semiconductor device, as set forth in claim 13, wherein the liner layer comprises oxide.

16. The semiconductor device, as set forth in claim 13, further comprising a contact etch stop layer.

17. The semiconductor device, as set forth in claim 13, further comprising a lightly-doped drain region on both sides of the gate and offset from the gate by the liner layer.

18. The semiconductor device, as set forth in claim 13, wherein the liner layer and the nitrogen-containing layer have a wet hydrofluoric acid etch rate of about 10 to about 1000 Å

per minute.

19. The semiconductor device, as set forth in claim 13, further comprising a silicide layer.

20. A semiconductor device, comprising:

a substrate;

a gate disposed on the substrate;

a source and drain formed in the substrate on both sides of the gate; and

a thin spacer having a first layer and a second layer formed on the sidewalls of the gate, wherein the first and second layers have comparable wet etch rates of at least 10 Å

per minute using the same etchant.

21. The semiconductor device, as set forth in claim 20, wherein the second layer comprises dopants selected from the group consisting of carbon, oxygen, fluorine, arsenic, boron, and chlorine.

22. The semiconductor device, as set forth in claim 20, wherein the first layer comprises an element selected from the group consisting of oxide, oxynitride, low k material, and high k material.

23. The semiconductor device, as set forth in claim 20, further comprising a contact etch stop layer.

24. The semiconductor device, as set forth in claim 20, further comprising a lightly-doped drain region on both sides of the gate and offset from the gate by the first layer.

25. The semiconductor device, as set forth in claim 20, wherein the first layer and the second layer have a wet hydrofluoric acid etch rate of about 10 to about 1000 Å

per minute.