Super trench MOSFET including buried source electrode and method of fabricating the same

• US 20050242392A1
• Filed: 04/30/2004
• Published: 11/03/2005
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Shi, Sharon, Terrill, Kyle, Chen, Kuo-In, Lui, Kam Hong, Pattanayak, Deva N., Xu, Robert, Yue, Christiana, Bai, Yuming
• Granted Patent: US 7,183,610 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

Claims

1. A trench-gate MOSFET comprising:

a semiconductor substrate having first and second trenches formed at a first surface thereof, said first and second trenches forming a mesa therebetween, said mesa comprising;

a source region of a first conductivity type located adjacent said first and second trenches at said first surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent said first and second trenches and forming a junction with said source region; and

a drift region of said first conductivity type located adjacent said first and second trenches and forming a junction with said body region, wherein said drift region has a substantially uniform doping concentration Nconst in a central portion of said drift region;

a drain region of said first conductivity type adjacent a second surface of said substrate opposite to said first surface, said drain region having a doping concentration greater than Nconst; and

a metal layer overlying said first surface of said substrate and being in electrical contact with said source region;

each of said first and second trenches comprising

an upper portion comprising a gate electrode, said gate electrode being separated from said body region by a gate oxide layer; and

a lower portion comprising a buried source electrode, said buried source electrode being electrically isolated from said drift region by a second oxide layer and from said gate electrode by a third oxide layer, said buried source electrode being electrically connected to said source region;

wherein a width of said mesa, a width of said trench, and said doping concentration Nconst in said drift region are established such that said drift region is fully depleted at a drain-to-source voltage equal to Vds but is not fully depleted at a drain-to-source voltage of less than Vds; and

wherein a thickness of said second oxide layer in cm is approximately equal to 10<sup>−

7</sup> times said voltage Vds in volts.

2. The MOSFET of claim 1 wherein Vds equals 60 volts, Nconst equals 5.1×

10¹⁶ cm<sup>−

3</sup>, said mesa width equals 1.0 μ

m, said trench width equals 0.8 μ

m, and said thickness of said second oxide layer equals 0.3 μ

m.

3. The MOSFET of claim 1 wherein Vds equals 90 volts, Nconst equals 2.7×

10¹⁶ cm<sup>−

3</sup>, said mesa width equals 1.4 μ

m, said trench width equals 1.3 μ

m, and said thickness of said second oxide layer equals 0.55 μ

m.

4. The MOSFET of claim 1 wherein Vds equals 100 volts, Nconst equals 2.0×

10¹⁶ cm<sup>−

3</sup>, said mesa width equals 2.0 μ

m, said trench width equals 1.4 μ

m, and said thickness of said second oxide layer equals 0.6 μ

m.

5. The MOSFET of claim 1 wherein Vds equals 150 volts, Nconst equals 1.1×

10<sup>16 −

3</sup>, said mesa width equals 2.9 μ

m, said trench width equals 2.2 μ

m, and said thickness of said second oxide layer equals 1.0 μ

m.

6. The MOSFET of claim 1 wherein Vds equals 200 volts, Nconst equals 7.5×

10¹⁶ cm<sup>−

3</sup>, said mesa width equals 3.1 μ

m, said trench width equals 3.4 μ

m, and said thickness of said second oxide layer equals 1.6 μ

m.

7. The MOSFET of claim 1 wherein Vds equals 250 volts, Nconst equals 4.5×

10¹⁵ cm<sup>−

3</sup>, said mesa width equals 4.4 μ

m, said trench width equals 4.6 μ

m, and said thickness of said second oxide layer equals 2.2 μ

m.

8. The MOSFET of claim 1 wherein said buried source electrode is electrically connected to said body region.

9. The MOSFET of claim 1 wherein said buried source electrode comprises doped polysilicon.

10. The MOSFET of claim 1 wherein said substrate comprises an epitaxial layer, said source region, said body region and said drift region being formed in said epitaxial layer.

11. The MOSFET of claim 8 wherein said trench extends to an interface between said epitaxial layer and into a portion of said substrate below said epitaxial layer.

12. The MOSFET of claim 1 wherein said gate oxide layer is thinner than said second oxide layer.

13. A trench-gate MOSFET comprising:

a semiconductor substrate having a trench formed at a first surface;

a source region of a first conductivity type located adjacent said trench at said first surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent said trench and forming a junction with said source region;

a drift region of said first conductivity type located adjacent said trench and forming a junction with said body region;

a drain region of said first conductivity type adjacent a second surface of said substrate opposite to said first surface; and

a metal layer overlying said first surface of said substrate and being in electrical contact with said source region;

said trench comprising

an upper portion comprising a gate electrode, said gate electrode being separated from said body region by a gate oxide layer; and

a lower portion comprising a buried source electrode, said buried source electrode being electrically isolated from said drift region by a second oxide layer and from said gate electrode by a oxide layer, said buried source electrode being electrically connected to said source region, said second oxide layer being substantially thicker than said gate oxide layer;

wherein said third oxide layer wraps around an upper portion of said buried source electrode so as to create a vertical overlap between said gate electrode and said buried source electrode.

14. The trench gate MOSFET of claim 13 wherein said junction between said body region and said drift region is located at a level above a level of an upper end of said second oxide layer and a lower end of said gate oxide layer.

15. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

depositing a mask layer over said first surface, said mask layer lining the walls and floor of said trench;

removing a portion of said mask layer adjacent the floor of said trench, remaining portions of said mask layer remaining attached to sidewalls of said trench;

etching said substrate through said bottom of said trench with said remaining portions of said mask layer remaining attached to sidewalls of said trench so as to form a cavity in said substrate;

heating said substrate with said remaining portions of said mask layer remaining attached to sidewalls of said trench so as to form a first dielectric layer in said cavity;

removing said remaining portions of said mask layer;

introducing a first layer of a conductive material into said cavity, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

heating said substrate so as form a second dielectric layer at an exposed surface of said conductive material and a gate dielectric layer along walls of said trench;

introducing a second layer of conductive material into said trench;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said gate dielectric layer;

forming a source region of said first conductivity type abutting said gate oxide layer and forming a junction with said body region;

covering said second layer of conductive material in said trench with a third dielectric layer;

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region and

forming an electrical connection between said first layer of conductive material and said source region.

16. The method of claim 15 wherein forming said trench comprises etching said substrate.

17. The method of claim 15 wherein depositing said mask layer comprises depositing silicon nitride.

18. The method of claim 15 wherein removing a portion of said mask layer comprises using a reactive ion etch process.

19. The method of claim 15 wherein said first dielectric layer comprises silicon dioxide.

20. The method of claim 15 wherein introducing said first layer of conductive material into said cavity comprises depositing doped polysilicon.

21. The method of claim 15 wherein introducing said second layer of conductive material into said trench comprises depositing doped polysilicon.

22. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

forming a first dielectric layer on the walls and bottom of said trench;

depositing a first layer of a conductive material in a lower portion of said trench, leaving an exposed portion of said first dielectric layer on the walls of an upper portion of said trench, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

removing said exposed portion of said first dielectric layer and a portion of said first dielectric layer that is laterally adjacent an upper portion of said first layer of conductive material, thereby exposing portions of lateral surfaces of said first conductive layer;

forming a second dielectric layer on the walls of said upper portion of said trench and on a top surface and said exposed portions of lateral surfaces of said first conductive layer;

depositing a second conductive layer in said upper portion of said trench, said first and second conductive layers vertically overlapping;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said second dielectric layer;

forming a source region of said first conductivity type abutting said second dielectric layer and forming a junction with said body region;

covering said second conductive layer with a third dielectric layer;

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region; and

forming an electrical connection between said first conductive layer and said source region.

23. The method of claim 22 wherein forming said trench comprises etching said substrate.

24. The method of claim 22 wherein said first dielectric layer comprises silicon dioxide.

25. The method of claim 22 wherein depositing said first layer of conductive material into said cavity comprises depositing doped polysilicon.

26. The method of claim 22 wherein depositing said second conductive layer into said trench comprises depositing doped polysilicon.

27. A trench-gated transistor formed in a semiconductor die, said transistor comprising:

an arrangement of annular trenches, each of said trenches being separated from an adjacent trench by an annular mesa;

a source metal layer and a gate metal layer, said gate metal layer comprising a plurality of gate metal legs that extend radially outward from a central area toward a perimeter of said die, said source metal layer comprising a plurality of sections located between said gate metal legs.

28. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a square annulus.

29. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a square annulus with rounded corners.

30. The trench-gated transistor of claim 29 wherein said transistor comprises four gate metal legs, each of said gate metal legs extending towards a corner of said die.

31. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a circular ring.

32. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a rectangular annulus.

33. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a rectangular annulus with rounded corners.

34. The trench-gated transistor of claim 27 wherein each of said trenches is in the shape of a hexagonal annulus.

35. The trench-gated transistor of claim 27 wherein the transistor is a MOSFET, said MOSFET comprising:

a source region of a first conductivity type located adjacent said trench at a first surface of said die, said source metal layer overlying said first surface of said die and being in electrical contact with said source region;

a body region of a second conductivity type opposite to said first conductivity type adjacent said trench and forming a junction with said source region;

a drift region of said first conductivity type located adjacent said trench and forming a junction with said body region;

a drain region of said first conductivity type adjacent a second surface of said die opposite to said first surface; and

said trench comprising

an upper portion comprising a gate electrode, said gate electrode being separated from said body region by a gate dielectric layer, said gate electrode being electrically connected to said gate metal layer; and

a lower portion comprising a buried source electrode, said buried source electrode being electrically isolated from said drift region by a second dielectric layer and from said gate electrode by a third dielectric layer, said buried source electrode being electrically connected to said source metal layer.

36. The trench-gated transistor of claim 35 wherein a peripheral trench is deeper than a trench located radially inward from said peripheral trench, said peripheral trench being lined with a fourth dielectric layer and containing a conductive material, said conductive material in said peripheral trench being electrically connected to said source metal layer.

37. The trench-gated transistor of claim 36 wherein said peripheral trench is wider than said trench radially inward from said peripheral trench.

38. The trench-gated transistor of claim 36 wherein at least one additional trench is deeper than said trench located radially inward from said peripheral trench.

39. A trench-gate MOSFET comprising:

a semiconductor substrate having a trench formed at a first surface;

a source region of a first conductivity type located adjacent said trench at said first surface;

a body region of a second conductivity type opposite to said first conductivity type adjacent said trench and forming a junction with said source region;

a drift region of said first conductivity type located adjacent said trench and forming a junction with said body region;

a drain region of said first conductivity type adjacent a second surface of said substrate opposite to said first surface; and

a metal layer overlying said first surface of said substrate and being in electrical contact with said source region;

said trench comprising

a source electrode in electrical contact with said metal layer;

a thick oxide layer lining the floor and lower portions of the sidewalls of said trench;

a multilayer structure lining the upper portions of the sidewalls of said trench, said multilayer comprising a first thin oxide layer in contact with said semiconductor substrate, a second thin oxide layer in contact with said source electrode, and a polysilicon layer separating said first and second thin oxide layers.

40. The trench gate MOSFET of claim 39 wherein said multilayer structure extends downward to a level below said junction between said body region and said drift region.

41. The trench gate MOSFET of claim 39 wherein a thickness of said multilayer structure is approximately the same as a thickness of said thick oxide layer.

42. A method of fabricating a MOSFET comprising:

forming a trench at a first surface of a semiconductor substrate, said substrate comprising dopant of a first conductivity type;

forming a thick dielectric layer on the walls and bottom of said trench;

depositing a first layer of a conductive material in said trench, said first layer of conductive material being electrically isolated from said substrate by said first dielectric layer;

removing an upper portion of said thick dielectric layer, said upper portion being located between said source electrode and said substrate, thereby forming a cavity between said substrate and said source electode;

forming a thin dielectric layer in said cavity, a first section of said thin dielectric layer abutting a wall of said trench, a second section of said thin dielectric layer abutting a wall of said source electrode;

depositing a second conductive layer in a space between said first and second thin dielectric layers;

forming a body region of a second conductivity type opposite to said first conductivity type in said substrate, said body region abutting said first section of said thin dielectric layer;

forming a source region of said first conductivity type abutting said first section of said thin dielectric layer and forming a junction with said body region;

covering said second conductive layer with a third dielectric layer; and

depositing a metal layer over said substrate, said metal layer being in electrical contact with said source region and said source electrode.