Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers

• US 20050242830A1
• Filed: 04/30/2004
• Published: 11/03/2005
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Linam, David Lawrence, Humphrey, Guy Harlan
• Granted Patent: US 7,088,129 B2
• Time in Patent Office: Days
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

A hybrid binary/thermometer code is employed to adjust the output impedance of a variable impedance output driver circuit having an impedance network comprising a plurality of impedance legs each programmably electrically connectable according to the hybrid binary/thermometer code in parallel between a voltage source and the signal pad. The plurality of impedance legs are partitioned into one or more set pairs of binary stepped impedance legs and corresponding thermometer stepped impedance legs. A binary set of calibration signals in the hybrid binary/thermometer code steps a given set of binary stepped impedance legs according to a binary code and a thermometer set of calibration signals in the hybrid binary/thermometer code steps the corresponding set of thermometer stepped impedance legs according to a thermometer code once per full count iteration of the binary set of calibration signals.

Claims

1. A variable impedance network for variably adjusting the output impedance of a node of a circuit, comprising:

one or more impedance legs electrically connected between a first voltage source and said node;

a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs;

a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs; and

a controller which generates said first set of calibration signals and said second set of calibration signals, wherein said controller steps said first set of calibration signals according to a binary code and steps said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals.

2. A variable impedance network in accordance with claim 1, wherein:

said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs is weighted increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

3. A variable impedance network in accordance with claim 2, wherein:

each of said first set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word.

4. A variable impedance network in accordance with claim 1, wherein:

each of said switchable impedance legs in said first set of impedance legs and said second set of impedance legs comprises a field effect transistor (FETs) sized to have a corresponding predetermined respective impedance.

5. A variable impedance network in accordance with claim 1, further comprising:

a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs;

a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs; and

wherein said controller generates said third set of calibration signals and said fourth set of calibration signals, wherein said controller steps said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code and steps said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals and said third set of calibration signals.

6. A variable impedance network in accordance with claim 5, wherein:

said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals represent bits with respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is weighted increasingly in order of the bit position of its corresponding calibration signal in the calibration word.

7. A variable impedance network in accordance with claim 5, wherein:

each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word.

8. A variable impedance network in accordance with claim 5, wherein:

each of said switchable impedance legs in said first set of impedance legs, said second set of impedance legs, said third set of impedance legs, and said fourth set of impedance legs comprises a field effect transistor (FETs) sized to have a corresponding predetermined respective impedance.

9. A method for variably adjusting the output impedance of a node of a circuit, said circuit comprising an impedance network interposed between a voltage source and said node, said impedance network comprising one or more impedance legs electrically connected between said first voltage source and said node, a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs, and a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs, said method comprising the steps of:

stepping said first set of calibration signals according to a binary code; and

stepping said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals.

10. A method in accordance with claim 9, wherein said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, said method further comprising:

weighting each of said first set of switchable impedance legs increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

11. A method in accordance with claim 9, wherein said first set of calibration signals and said second set of calibration signals represent bits with respective predetermined bit positions in a calibration word, said method further comprising:

weighting each of said first set of switchable impedance legs according to a binary weighting scheme in order of the bit position of its corresponding calibration signal in the calibration word.

12. A method in accordance with claim 9, wherein said impedance network further comprises a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs, and a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs, said method further comprising the steps of:

stepping said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code; and

stepping said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals and said third set of calibration signals.

13. A method in accordance with claim 12, said method further comprising:

weighting each of said first set of switchable impedance legs and said third set of impedance legs increasingly in order of the respective predetermined bit position of its corresponding calibration signal in the calibration word.

14. A method in accordance with claim 13, said method further comprising+

weighting each of said first set of switchable impedance legs according to a binary weighting scheme in order of the bit position of its corresponding calibration signal in the calibration word.

15. A variable impedance network for variably adjusting the output impedance of a node of a circuit, comprising:

one or more impedance legs electrically connected between a first voltage source and said node;

a first set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a first set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said first set of switchable impedance legs;

a second set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a second set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said second set of switchable impedance legs;

a third set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a third set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said third set of switchable impedance legs;

a fourth set of switchable impedance legs programmably electrically connectable between said voltage source and said node by a fourth set of calibration signals each of which corresponds to a respective one or more of said switchable impedance legs in said fourth set of switchable impedance legs;

wherein said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals represent bits with different respective predetermined bit positions in a calibration word, and wherein each of said first set of switchable impedance legs and each of said third set of switchable impedance legs is binary weighted according to the bit position of its corresponding calibration signal in the calibration word; and

a controller which generates said first set of calibration signals, said second set of calibration signals, said third set of calibration signals, and said fourth set of calibration signals;

wherein said controller steps said first set of calibration signals according to a binary code and steps said second set of calibration signals according to a thermometer code once per full count iteration of said first set of calibration signals, and steps said first set of calibration signals and said third set of calibration signals, taken as a combination, according to a binary code and steps said fourth set of calibration signals according to a thermometer code once per full count iteration of said combination of said first set of calibration signals and said third set of calibration signals.

16. A method for stepping a hybrid binary/thermometer code, said code comprising a first set of binary bits each with a predetermined bit position in said code and a first set of thermometer bits each with a different predetermined bit position in said code, said method comprising the steps of:

for each incrementing step of said hybrid binary/thermometer code;

incrementing said first set of binary bits according to a binary increment; and

if said first set of thermometer bits is not fully incremented, incrementing said first set of thermometer bits according to a thermometer code increment upon overflow of said first set of binary bits.

17. A method in accordance with claim 16, further comprising the steps of:

for each decrementing step of said hybrid binary/thermometer code;

decrementing said first set of binary bits according to a binary decrement; and

if said first set of thermometer bits is not fully decremented, decrementing said first set of thermometer bits according to a thermometer code decrement upon underflow of said first set of binary bits.

18. A method in accordance with claim 16, said hybrid binary/thermometer code comprising a next set of binary bits and a corresponding next set of thermometer bits, each of said next set of binary bits and said next set of thermometer bits defined by different predetermined bit positions in said hybrid binary/thermometer code from one another and from said first set of binary bits and said first set of thermometer bits, said method further comprising the steps of:

for each incrementing step of said hybrid binary/thermometer code;

if said first set of thermometer bits is incrementally saturated, incrementing said first set of binary bits and said next set of binary bits, taken in combination, according to a binary increment; and

incrementing said next set of thermometer bits according to a thermometer code increment upon overflow of said combination of said first set of binary bits and said next set of binary bits.

19. A method in accordance with claim 18, further comprising the steps of:

for each decrementing step of said hybrid binary/thermometer code;

decrementing said combination of said first set of binary bits and said next set of binary bits according to a binary decrement; and

if said first set of thermometer bits and said next set of thermometer bits, treated in combination as a thermometer code, is not fully decremented, decrementing said combination of said first set of thermometer bits and said next set of thermometer bits according to a thermometer code decrement upon underflow of said combination of said first set of binary bits and said next set of binary bits.

20. A method for stepping a hybrid binary/thermometer code, said code comprising a first set of binary bits each with a predetermined bit position in said code and a first set of thermometer bits each with a different predetermined bit position in said code, said method comprising the steps of:

for each incrementing step of said hybrid binary/thermometer code;

incrementing said first set of binary bits according to a binary increment; and

if said first set of thermometer bits is not fully incremented, incrementing said first set of thermometer bits according to a thermometer code increment upon overflow of said first set of binary bits.

21. A method in accordance with claim 20, further comprising the steps of:

for each decrementing step of said hybrid binary/thermometer code;

decrementing said first set of binary bits according to a binary decrement; and

if said first set of thermometer bits is not fully decremented, decrementing said first set of thermometer bits according to a thermometer code decrement upon underflow of said first set of binary bits.

22. A method in accordance with claim 20, said hybrid binary/thermometer code comprising a next set of binary bits and a corresponding next set of thermometer bits, each of said next set of binary bits and said next set of thermometer bits defined by different predetermined bit positions in said hybrid binary/thermometer code from one another and from said first set of binary bits and said first set of thermometer bits, said method further comprising the steps of:

for each incrementing step of said hybrid binary/thermometer code;

if said first set of thermometer bits is incrementally saturated, incrementing said first set of binary bits and said next set of binary bits, taken in combination, according to a binary increment; and

incrementing said next set of thermometer bits according to a thermometer code increment upon overflow of said combination of said first set of binary bits and said next set of binary bits.

23. A method in accordance with claim 22, further comprising the steps of:

for each decrementing step of said hybrid binary/thermometer code;

decrementing said combination of said first set of binary bits and said next set of binary bits according to a binary decrement; and

if said first set of thermometer bits and said next set of thermometer bits, treated in combination as a thermometer code, is not fully decremented, decrementing said combination of said first set of thermometer bits and said next set of thermometer bits according to a thermometer code decrement upon underflow of said combination of said first set of binary bits and said next set of binary bits.