System monitor in a programmable logic device
First Claim
Patent Images
1. A programmable logic device, comprising:
- a system monitor, the system monitor including;
channel inputs including analog inputs;
selection circuitry coupled to the channel inputs, the selection circuitry having a channel output;
an analog-to-digital converter having an analog input and a digital output;
an interface having storage devices, the storage devices for storing control information and data, the interface including a dynamic reconfiguration port and control logic;
the analog-to-digital converter configurable responsive to a first portion of the control information;
the selection circuitry configured to selectively couple a channel input of the channel inputs to the channel output responsive to a second portion of the control information; and
the analog-to-digital converter coupled to the channel output at the analog input and coupled at the digital output to the storage devices.
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Abstract
Method and apparatus for a system monitor (20) embedded in a programmable logic device (10, 50, 60) are described. The system monitor (20) includes a dynamic reconfiguration port interface (205) for configuring or reconfiguring the system monitor (20) during operation thereof. The system monitor (20) includes an analog-to-digital converter (200) which is reconfigurable responsive to input via a dynamic reconfiguration port (201).
63 Citations
54 Claims
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1. A programmable logic device, comprising:
a system monitor, the system monitor including;
channel inputs including analog inputs;
selection circuitry coupled to the channel inputs, the selection circuitry having a channel output;
an analog-to-digital converter having an analog input and a digital output;
an interface having storage devices, the storage devices for storing control information and data, the interface including a dynamic reconfiguration port and control logic;
the analog-to-digital converter configurable responsive to a first portion of the control information;
the selection circuitry configured to selectively couple a channel input of the channel inputs to the channel output responsive to a second portion of the control information; and
the analog-to-digital converter coupled to the channel output at the analog input and coupled at the digital output to the storage devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A method for configuration of a system monitor, comprising:
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resetting a system monitor after powering up a host programmable logic device;
waiting for the programmable logic device to initialize;
activating reference generation circuits and at least one temperature sensor; and
entering a temperature sensing mode of the system monitor, the temperature sensing mode being independent of configuration of configuration memory cells of the programmable logic device. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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47. A programmable logic device, comprising:
a system monitor, the system monitor including;
channel inputs including analog inputs;
selection circuitry coupled to the channel inputs, the selection circuitry having a channel output;
an analog-to-digital converter having an analog input and a digital output;
an interface having storage devices, the storage devices for storing control information and data, the interface including control logic and interface logic;
the analog-to-digital converter configurable responsive to a first portion of the control information;
the selection circuitry configured to selectively couple a channel input of the channel inputs to the channel output responsive to a second portion of the control information; and
the analog-to-digital converter coupled to the channel output at the analog input and coupled at the digital output to the storage devices. - View Dependent Claims (48)
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49. A system monitor circuit in an integrated circuit comprising:
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an analog-to digital converter (ADC) configured to monitor a plurality of sensors;
a calibration circuit for calibrating an output of the ADC using a set value in a first register;
a filter circuit for filtering an output of the calibration circuit or an output of the ADC; and
a alarm circuit configured to determine an alarm condition by comparing the output of the calibration circuit or an output of the ADC or an output of the filter circuit with a set value in a second register. - View Dependent Claims (50, 51, 52, 53, 54)
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Specification