Thin film transistor array substrate and fabricating method thereof

• US 20050243228A1
• Filed: 04/29/2005
• Published: 11/03/2005
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Choi, Seung Chan, Lee, Hyun Kyu, Jeong, See Hwa
• Granted Patent: US 7,495,733 B2
• Time in Patent Office: Days
• US Class Current: 349/42
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]

Abstract

A liquid crystal display and a fabricating method thereof for improving an aperture ratio are disclosed. A liquid crystal display (LCD) according to the present invention includes a gate line, a data line and a common line on the thin film transistor array substrate, the gate line crossing the data line to define a pixel region; a thin film transistor near the crossing of the gate line and the data line; a common electrode connected to the common line in the pixel region; and a pixel electrode connected to the thin film transistor in the pixel area for forming an in-plane electric field in association with the common electrode during an operation of the LCD, wherein an edge of the pixel electrode overlaps the common line with at least one insulating layer therebetween, and an edge of the common electrode overlaps the pixel electrode with said at least one insulating layer therebetween.

Claims

1. A thin film transistor array substrate, comprising:

a gate line;

a data line crossing the gate line to define a pixel area;

a common line formed in parallel to the data line;

a thin film transistor near the crossing of the gate line and the data line;

a common electrode connected to the common line and formed in parallel to the gate line at the pixel area; and

a pixel electrode connected to the thin film transistor for forming a horizontal electric field with respect to the common electrode,

wherein at least one edge of the pixel electrode overlaps the common line with at least one insulating layer therebetween, and at least one edge of the common electrode overlaps the pixel electrode with said at least one insulating layer therebetween.

2. The thin film transistor array substrate according to claim 1, wherein the pixel electrode includes:

a vertical part connected to the thin film transistor in parallel to the data line and overlapping one edge of the common electrode; and

a finger part formed on a plane different from the vertical part in such a manner to be overlapped with the vertical part, thereby making a horizontal electric field with respect to the pixel electrode.

3. The thin film transistor array substrate according to claim 2, wherein said vertical part of the pixel electrode and said common line are formed of the same metal on the same plane, and said finger part of the pixel electrode and said common electrode are formed of the same metal on the same plane.

4. The thin film transistor array substrate according to claim 3, wherein said vertical part of the pixel electrode and said common line are formed of a gate metal on the substrate, and said finger part of the pixel electrode and said common electrode is formed of a transparent conductive material on said at least one insulating layer in such a manner to cover the horizontal part of the pixel electrode and the common line.

5. The thin film transistor array substrate according to claim 2, wherein said common line is formed separately for each pixel area with the gate line therebetween.

6. The thin film transistor array substrate according to claim 5, further comprising:

a first connection pattern extended from the common electrode positioned at the outermost portion of said pixel area to connect the common lines separated for each pixel area; and

a second connection pattern being in contact with the drain electrode and the pixel electrode to connect them to each other.

7. The thin film transistor array substrate according to claim 6, further comprising:

a first contact hole for exposing the drain electrode to contact the second connection pattern with the drain electrode;

a second contact hole for exposing the vertical part of the pixel electrode to contact the second connection pattern with the vertical part of the pixel electrode;

a third contact hole for exposing the vertical part of the pixel electrode to contact the vertical part of the pixel electrode with the finger part of the pixel electrode; and

a fourth contact hole for exposing the common line to contact the common line with the common electrode.

8. The thin film transistor array substrate according to claim 1, further comprising:

a storage capacitor having a lower storage electrode protruded from the common line, and an upper storage electrode overlapping the lower storage electrode with at least one layer of insulating layer therebetween and connected to the pixel electrode.

9. The thin film transistor array substrate according to claim 8, wherein said finger part of the pixel electrode and said common electrode positioned between the lower storage electrode and the pre-stage gate line are formed in parallel to each other in a first direction, and said finger part of the pixel electrode and said common electrode positioned between the lower storage electrode and the current-stage gate line are formed in parallel to each other in a second direction that is different from said first direction.

10. A method of fabricating a liquid crystal display (LCD) comprising:

forming a first conductive pattern group including a gate line, a gate electrode connected to the gate line, a common line between the gate line and a pre-stage gate line in such a manner to cross the gate line and a vertical part of a pixel electrode parallel to the common line on a substrate;

forming a gate insulating layer on the substrate provided with the first conductive pattern group;

forming a semiconductor pattern on the gate insulating layer;

forming a data line crossing the gate line to define a pixel area, a source electrode connected to the data line and a drain electrode opposed to the source electrode on the gate insulating layer provided with the semiconductor pattern;

forming a protective layer on the substrate provided with the data line, the source electrode and the drain electrode; and

forming a common electrode connected to the common line and overlapping the vertical part of the pixel electrode and a finger part of the pixel electrode overlapping the common line, the common electrode and the finger part of the pixel electrode forming a horizontal electric field during an operation of the LCD.

11. The method according to claim 10, further comprising:

forming a first connection pattern extended from the common electrode positioned at the outermost portion of said pixel area to connect the common lines separated for each pixel area; and

forming a second connection pattern being in contact with the drain electrode and the pixel electrode to connect them to each other.

12. The method according to claim 11, wherein forming the protective layer further includes:

forming a first contact hole passing through the protective layer to expose the drain electrode, thereby contacting the second connection pattern with the drain electrode;

forming a second contact hole passing through the gate insulating layer and the protective layer to expose the common line, thereby contacting the vertical part of the pixel electrode and the second connection pattern;

forming a third contact hole passing through the gate insulating layer and the protective layer to expose the vertical part of the pixel electrode, thereby contacting the vertical part of the pixel electrode with the finger part thereof; and

forming a fourth contact hole passing through the gate insulating layer and the protective layer to expose the common line, thereby contacting the common line with the common electrode.

13. The method according to claim 10, further comprising:

forming a storage capacitor having a lower storage electrode extended from the common line, and an upper storage electrode overlapping the lower storage electrode with at least one layer of insulating layer therebetween and connected to the pixel electrode.

14. The method according to claim 13, wherein forming the common electrode and the finger part of the pixel electrode on the protective layer includes:

forming said finger part of the pixel electrode and said common electrode positioned between the lower storage electrode and the pre-stage gate line in parallel to each other in a first direction; and

forming said common electrode positioned between the lower storage electrode and the gate line in parallel to each other in a second direction that is different from said first direction.

15. A liquid crystal display (LCD) comprising:

a gate line, a data line and a common line on a substrate, the gate line crossing the data line to define a pixel region;

a thin film transistor near the crossing of the gate line and the data line;

a common electrode connected to the common line in the pixel area; and

a pixel electrode connected to the thin film transistor in the pixel region for forming an in-plane electric field in association with the common electrode during an operation of the LCD,

wherein an edge of the pixel electrode overlaps the common line with at least one insulating layer therebetween, and an edge of the common electrode overlaps the pixel electrode with said at least one insulating layer therebetween.

16. The display according to claim 15, wherein the pixel electrode includes:

a vertical part connected to the thin film transistor and being overlapped with said edge of the common electrode; and

a finger part formed on a plane different from the vertical part and electrically connected to the vertical part.

17. The display according to claim 16, wherein said vertical part of the pixel electrode and said common line are formed of the same metal on the same plane, and said finger part of the pixel electrode and said common electrode are formed of the same metal on the same plane.

18. The display according to claim 16, wherein said common line is electrically connected to a common line in an adjacent pixel region via a connecting pattern.

19. The display according to claim 15, further comprising:

a storage capacitor having a lower storage electrode extended from the common line, and an upper storage electrode connected to the pixel electrode.

20. The display according to claim 19, wherein said finger part of the pixel electrode and said common electrode between the lower storage electrode and a gate line in an adjacent pixel region are formed in parallel to each other in a first direction, and said finger part of the pixel electrode and said common electrode positioned between the lower storage electrode and the gate line are formed in parallel to each other in a second direction that is different from said first direction.