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Semiconductor memory device

  • US 20050243599A1
  • Filed: 07/23/2003
  • Published: 11/03/2005
  • Est. Priority Date: 05/16/2003
  • Status: Active Grant
First Claim
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1. A semiconductor memory device, which includes:

  • a cell block composed of several series-connected units having a ferroelectric capacitor and a cell transistor parallel-connected to the ferroelectric capacitor; and

    a select transistor connected to an end of the cell block, the semiconductor memory device comprising;

    a semiconductor substrate;

    a plurality of first impurity diffusion layers formed on the surface of the semiconductor substrate in a state of being mutually separated along a first direction, having a first area, and constituting a source/drain diffusion layer of the cell transistor;

    a second impurity diffusion layer formed on the surface of the semiconductor substrate in a state of being separated from the first impurity diffusion layer of an end of the first impurity diffusion layers, having a second area, and constituting a source/drain diffusion layer of the cell transistor;

    a plurality of first gate electrodes provided on the semiconductor substrate with a gate insulating film interposed therebetween between the first impurity diffusion layers along a second direction, and constituting a gate of the cell transistor;

    a second gate electrode provided on the semiconductor substrate with a gate insulating film interposed therebetween between the first impurity diffusion layer of the end and the second impurity diffusion layer along a second direction, and constituting a gate of the select transistor; and

    a contact electrically connecting a bit line and the second impurity diffusion layer.

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