Highly compact Eprom and flash EEprom devices
First Claim
1. A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
- forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed.
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Accused Products
Abstract
Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
126 Citations
21 Claims
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1. A method of forming a split-channel electrically programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having sidewalls and being electrically isolated by a gate dielectric layer from said substrate, forming a spacer immediately adjacent only one sidewall of said floating gate and extending a controlled distance over said substrate surface, forming source and drain regions in said substrate by using said floating gate and said spacer as a mask, whereby a channel region is formed in the substrate under the masked region between the source and drain regions, removing said spacer, and forming a control gate extending over at least a portion of the floating gate and substrate channel region that was occupied by said spacer, said control gate being electrically insulated from said floating gate and said substrate, whereby a split-channel electrically programmable read only memory transistor is formed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of forming a split-channel flash electrically erasable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side, forming a control gate extending over at least a portion of the floating gate and said second channel region, said control gate being electrically insulated from said floating gate and said substrate, forming regions of a tunnel erase dielectric layer on each of opposite ends of said floating gate, and forming a pair of parallel erase gates extending between the source and drain regions and across the opposite ends of the floating gate on the tunnel dielectric layers. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method of forming a split-channel flash electrically eraseable and programmable read only memory transistor on a semiconductor substrate surface, comprising the steps of:
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forming on said surface a floating gate having opposite sides and opposite ends, said floating gate being electrically insulated from said substrate by a gate dielectric layer, forming in said substrate a drain region adjacent one side of said floating gate and a source region spaced apart from an opposite side of said floating gate, thereby to form a channel region between the source and drain that has a first channel region under the floating gate a second channel region between the source region and the opposite floating gate side, forming a region of a tunnel erase dielectric layer on a portion of the surface of said floating gate, forming an erase gate extending across the floating gate on the tunnel dielectric layer and across the second channel region of the substrate with a dielectric layer therebetween, and forming over and around the erase gate a control gate extending across the floating gate and second channel region, said control gate being electrically insulated from said floating gate and said substrate.
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21-149. -149. (canceled)
Specification