Semiconductor integrated circuit device including first, second and third gates

• US 20050243603A1
• Filed: 02/22/2005
• Published: 11/03/2005
• Est. Priority Date: 07/14/1999
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kobayashi, Takashi, Kume, Hitoshi, Kobayashi, Naoki, Kimura, Katsutaka, Kurata, Hideaki, Saeki, Shunichi
• Granted Patent: US 7,180,774 B2
• Time in Patent Office: Days
• US Class Current: 365/185.170
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.

Claims

1. A semiconductor integrated circuit device, comprising:

a plurality of word lines; and

a plurality of memory cells,

wherein each of said memory cells includes a floating gate formed over a semiconductor substrate through a first insulator film, a control gate formed over said floating gate through a second insulator film and an assist gate formed over a side surface of said floating gate through a third insulator film,

wherein each of said assist gates is connected in a first direction,

wherein each of said control gates is connected in a second direction intersected with the first direction to form said word lines, and

wherein one of said assist gates functioning to generate hot electrons is alternately arranged in said second direction with another one of said assist gates functioning to prevent a non-selected memory cell from a write error in a write operation.

2. The semiconductor integrated circuit device according to claim 1,

wherein a memory array having said plurality of memory cells is structured such that the write operation is performed for all said memory cells connected with one word line by repeating the write operation several times.

3. The semiconductor integrated circuit device according to claim 1,

wherein memory cells which are selected in one write operation, among said memory cells connected with one word line, are periodically arranged throughout said non-selected memory cells.

4. The semiconductor integrated circuit device according to claim 3,

wherein said one write operation performs the write in at least one memory cell among said selected memory cells.

5. The semiconductor integrated circuit device according to claim 3,

wherein said selected memory cells are periodically arranged throughout the memory cells.

6. The semiconductor integrated circuit device according to claim 1,

wherein a write is performed for all memory cells for which a write operation and a read operation can be performed among said memory cells connected with one word line by operating said assist gate which functions to generate the hot electrons as a gate to prevent said non-selected memory cells from the write error, and by operating said assist gate which functions to prevent said non-selected memory cells from the write error as a gate to generate the hot electrons.

7. The semiconductor integrated circuit device according to claim 1, wherein a memory cell array structured by said plurality of memory cells includes a virtual ground type memory cell array.

8. The semiconductor integrated circuit device according to claim 1,

wherein said assist gates functioning to prevent said non-selected memory cells from the write error prevent the write error by making a channel within said semiconductor substrate under said assist gates during an off-state.

9. A semiconductor integrated circuit device, comprising:

a plurality of word lines; and

a plurality of memory cells,

wherein each of said memory cells includes a floating gate formed over a semiconductor substrate through a first insulator film, a control gate formed over said floating gate through a second insulator film and an assist gate formed over a side surface of said floating gate through a third insulator film,

wherein each of said assist gates is connected in a first direction,

wherein each of said control gates is connected in a second direction intersected with the first direction to form said word lines,

wherein said memory cells to be selected by one write operation in one word line include first memory cells and second memory cells arranged on a location where said first memory cells are separated from said second memory cells in the second direction,

wherein said first and second memory cells are alternately arranged in the second direction, and

wherein, in the one write operation, said assist gates arranged between said floating gate and first sources of said first memory cells function as gates to generate hot electrons, and said assist gates arranged between drains of said first memory cells and second sources of said second memory cells arranged on said drain side function as gates to prevent said non-selected memory cells from a write error.

10. The semiconductor integrated circuit device according to claim 9

wherein a memory cell array having said plurality of memory cells is structured such that the write operation is performed for all said memory cells connected with one of said word lines by repeating the write operation several times.

11. The semiconductor integrated circuit device according to claim 9,

wherein said first and second memory cells are arranged throughout one memory cell.

12. The semiconductor integrated circuit device according to claim 9,

wherein said one write operation performs the write in at least one of said first and second memory cells.

13. The semiconductor integrated circuit device according to claim 9,

wherein a write is performed for all memory cells for which a write operation and a read operation can be performed among said memory cells connected with one word line by operating said assist gate which functions to generate the hot electrons as a gate to prevent said non-selected memory cells from the write error, and by operating said assist gate which functions to prevent said non-selected memory cells from the write error as a gate to generate the hot electrons.

14. The semiconductor integrated circuit device according to claim 9,

wherein a memory cell array structured by said plurality of memory cells includes a virtual ground type memory cell array.

15. The semiconductor integrated circuit device according to claim 9,

wherein said assist gates arranged between drains of said first memory cells and second sources of said second memory cells arranged on said drain side of said first memory cells prevent the write error by making a channel within said semiconductor substrate under said assist gates during an off-state.

16. A semiconductor integrated circuit device, comprising:

a plurality of word lines; and

a plurality of memory cells,

wherein each of said memory cells includes a floating gate formed over a semiconductor substrate through a first insulator film, a control gate formed over said floating gate through a second insulator film and an assist gate formed over a side surface of said floating gate through a third insulator film,

wherein each of said assist gates is connected in a first direction,

wherein each of said control gates is connected in a second direction intersected with the first direction to form said word lines,

wherein said memory cells to be selected by one write operation in one word line include first memory cells and second memory cells arranged on a location where said first memory cells are separated from said second memory cells in the second direction,

wherein said first and second memory cells are alternately arranged in the second direction, and

wherein in one write operation, said assist gates of said first memory cells and said assist gates of said second memory cells function as gates to generate hot electrons, and at least one said assist gate functioning as a gate to prevent said non-selected memory cells from a write error exists between said assist gates of said first memory cells and said assist gates of said second memory cells.

17. The semiconductor integrated circuit device according to claim 16

wherein a memory cell array having said plurality of memory cells is structured such that the write operation is performed for all said memory cells connected with one word line by repeating the write operation several times.

18. The semiconductor integrated circuit device according to claim 16,

wherein said first and second memory cells are arranged through one memory cell.

19. The semiconductor integrated circuit device according to claim 16,

wherein said one write operation performs the write in at least one of said first and second memory cells.

20. The semiconductor integrated circuit device according to claim 16,

wherein a write is performed for all memory cells for which a write operation and a read operation can be performed among said memory cells connected with one word line by operating said assist gate which functions to generate the hot electrons as a gate to prevent said non-selected memory cells from the write error, and by operating said assist gate which functions to prevent said non-selected memory cells from the write error as a gate to generate the hot electrons.

21. The semiconductor integrated circuit device according to claim 16,

wherein a memory cell array structured by said plurality of memory cells includes a virtual ground type memory cell array.

22. The semiconductor integrated circuit device according to claim 16,

wherein said assist gates functioning as gates to prevent said non-selected memory cells from the write error prevent the write error by making a channel within said semiconductor substrate under said assist gate turn an off-state.

23. A semiconductor integrated circuit device, comprising:

a plurality of word lines; and

a plurality of memory cells,

wherein each of said memory cells includes a floating gate formed over a semiconductor substrate through a first insulator film, a control gate formed over said floating gate through a second insulator film and an assist gate formed over a side surface of said floating gate through a third insulator film,

wherein each of said assist gates is connected in a first direction,

wherein each of said control gates is connected in a second direction intersected with the first direction to form said word lines,

wherein said plurality of memory cells arranged on locations separately from one another are structured such that said memory cells are selected by one write operation in one word line, and

wherein in the one write operation once, said assist gates of said selected first memory cells function as gates to generate hot electrons, and said assist gates functioning as gates which prevent a current between said selected memory cells exist between said assist gates of said plurality of selected memory cells.

24. The semiconductor integrated circuit device according to claim 23,

wherein a memory cell array having said plurality of memory cells is structured such that the write operation is performed for all said memory cells connected with one of said word lines by repeating the write operation several times.

25. The semiconductor integrated circuit device according to claim 23,

wherein said selected memory cells in the one write operation, among said memory cells connected with the one word line, are periodically arranged throughout said non-selected memory cells.

26. The semiconductor integrated circuit device according to claim 23,

wherein said one write operation performs the write in at least one memory cell among said memory cells to be selected.

27. The semiconductor integrated circuit device according to claim 23,

wherein said selected memory cells are periodically arranged throughout the memory cells.

28. The semiconductor integrated circuit device according to claim 23, wherein a write is performed for all memory cells for which a write operation and a read operation can be performed among said memory cells connected with one word line by operating said assist gate which functions to generate the hot electrons as a gate to prevent the flow of current between said memory cells and by operating said assist gate which functions to prevent the flow of current between said selected memory cells, as a gate to generate the hot electrons.

29. The semiconductor integrated circuit device according to claim 23,

wherein a memory cell array structured by said plurality of memory cells includes a virtual ground type memory cell array.

30. The semiconductor integrated circuit device according to claim 23,

wherein said assist gate functioning to prevent a current flow between said selected memory cells is a gate to make a channel within said semiconductor substrate under said assist gates during an off-state.