Memory device tester and method for testing reduced power states

• US 20050243638A1
• Filed: 07/01/2005
• Published: 11/03/2005
• Est. Priority Date: 09/02/1999
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Hyslop, Adin E., Harrington, Matthew R., Huynh, Van C.
• Granted Patent: US 7,161,866 B2
• Time in Patent Office: Days
• US Class Current: 365/230.30
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/024 in decoders
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.

Claims

1. A memory device tester comprising:

a receptacle for receiving a memory device;

at least one control bus coupled to the receptacle for communicating with the memory device;

a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, the plurality of commands comprising;

a first command adapted to cause the memory device to enter a reduced power state;

a first current calibration sequence including at least one calibration (CAL) command;

a second command adapted to cause the memory device to leave the reduced power state; and

a second current calibration sequence including at least one calibration (CAL) command.

2. A memory device tester comprising:

a receptacle for receiving a memory device;

at least one control bus coupled to the receptacle for communicating with the memory device;

a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, the plurality of commands comprising;

a first command adapted to cause the memory device to enter a reduced power state;

a first current calibration sequence including at least one calibration (CAL) command and at least one current calibration sample (CAL/SAM) command;

a second command adapted to cause the memory device to leave the reduced power state; and

a second current calibration sequence including at least one calibration (CAL) command.

3. A memory device tester comprising:

a receptacle for receiving a memory device;

at least one control bus coupled to the receptacle for communicating with the memory device;

a processing unit coupled to the at least one control bus for sending a plurality of commands to the memory device, the plurality of commands comprising;

a first command adapted to cause the memory device to enter a reduced power state;

a first current calibration sequence including at least one calibration (CAL) command;

a second command adapted to cause the memory device to leave the reduced power state; and

a second current calibration sequence including at least one calibration (CAL) command and at least one current calibration sample (CAL/SAM) command.