Information processing device, processor, processor control method, information processing device control method and cache memory

• US 20050246506A1
• Filed: 09/10/2004
• Published: 11/03/2005
• Est. Priority Date: 04/30/2004
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Ukai, Masaki
• Granted Patent: US 7,853,756 B2
• Time in Patent Office: Days
• US Class Current: 711/152
• CPC Class Codes: G06F 2209/521 Atomic
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3009 Thread control instructions
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.

Claims

1. A method for controlling a processor which accesses information of a storage device through cache memory, comprising:

a first step of reading information stored in a target address or an address range of the storage device and monitoring whether there is an update access to the address or the address range from another processor;

a second step of entering the processor into a suspense status; and

a third step of releasing the suspense status using the occurrence of the update access as a trigger.

2. The processor control method according to claim 1, wherein

if the occurrence of the update access is detected between said first and second steps, the execution of said second step is suppressed.

3. The processor control method according to claim 1, wherein

part of cache management information for managing the cache memory comprises discrimination information for discriminating the storage area of the cache memory corresponding to the specific storage area of the storage device, and

in said first step the storage area of the cache memory, corresponding to the address or address range of the storage device accessed is designated as a monitor target by attaching the discrimination information, and

in said third step the suspense status is released using the occurrence of the nullification or rewriting of the information about the storage area of the cache memory as a trigger.

4. The processor control method according to claim 1, wherein

in said second step, the clock supply to the processor is suspended, and

in said third step, the clock supply is resumed.

5. A method for controlling a processor which accesses information of a storage device through cache memory, comprising:

a first step of detecting an instruction string composed of at least one of a first instruction to collectively read and update information in a target address or an address range of the storage device and a second instruction to read information about the address or address range;

a second step of monitoring whether there is an update access to the address or the address range from another processor and also entering the processor into a suspense status using detection of the instruction string as a trigger; and

a third step of releasing the suspense status using the occurrence of the update access to the address or address range from another processor as a trigger.

6. The processor control method according to claim 5, wherein

part of cache management information for managing the cache memory comprises discrimination information for discriminating the storage area of the cache memory corresponding to the specific storage area of the storage device, and

in the first step, the storage area of the cache memory, corresponding to the address or address range of the storage device accessed is designated as a monitor target by attaching the discrimination information, and

in said third step, the suspense status is released using the occurrence of the nullification or rewriting of the information about the storage area of the cache memory as a trigger.

7. The processor control method according to claim 5, wherein

in said second step, the clock supply to the processor is suspended, and

in said third step, the clock supply is resumed.

8. An information processing device, comprising:

an instruction control unit;

cache memory inserted between the instruction control unit and a storage device;

a load instruction to read information from the storage device into the instruction control unit; and

a monitor trigger setting function to set the monitor start trigger of a specific storage area of the storage device, including a target access area of the load instruction.

9. An information processing device, comprising:

an instruction control unit;

cache memory inserted between the instruction control unit and a storage device;

a load instruction to read information from the storage device into the instruction control unit; and

a writing detection function to monitor a specific storage area of the storage device, including a target access area of the load instruction and to detect a possibility that information may be written into the specific storage area.

10. The information processing device according to claim 9, wherein

part of cache management information for managing said cache memory comprises discrimination information for discriminating the storage area of said cache memory corresponding to the specific storage area of the storage device, and the storage area of the cache memory, to which the discrimination information is attached, is designated as the monitor target of said writing detection function.

11. The information processing device according to claim 9, wherein

said writing detection function comprises at least one register, and

a monitor address indicating the specific storage area is set in said register, and the specific storage area is monitored by comparing the monitor address with an access address to all segments of cache memory.

12. The information processing device according to claims 9, wherein

if there is an instruction to nullify or rewrite information stored corresponding to the specific storage area of said cache memory, it is determined that there is a possibility of writing into the specific storage area.

13. An information processing device, comprising:

an instruction control unit;

cache memory inserted between the instruction control unit and a storage device;

a load instruction to read information from the storage device into the instruction control unit; and

a suspense instruction to enter the instruction control unit into a suspense status and to release the suspense status using detection of a possibility of writing the information into the specific storage area of the storage device, including a target access area of the load instruction as a trigger.

14. The information processing device according to claim 13, further comprising

a clock supply control function to suspend and resume clock supply to said instruction control unit in synchronization with entry to the suspense status by said suspense instruction and release from the suspense status.

15. An information processing device provided with an exclusive control mechanism for exclusively controlling access to shared memory of a plurality of instruction control units by rewriting specific information in a specific area of the shared memory, comprising

a clock supply control function to suspend clock supply to the relevant instruction control unit while one of the plurality of instruction control units is waiting for rewriting of the specific information by another instruction control unit as a trigger.

16. An information processing device, comprising

a plurality of logical or physical instruction control units;

cache memory which is inserted between each of the instruction control unit and a storage device and is shared by the plurality of instruction control units; and

a writing detection function to notify other instruction control units of a fact that one of the plurality of instruction control units has written information into a specific storage area of the storage device.

17. The information processing device according to claim 16, wherein

each of said instruction control units comprises

a suspense instruction to enter the relevant instruction control unit into a suspense status and to release the suspense status using notification from said writing detection function as a trigger.

18. A processor with an instruction set, said instruction set comprising:

a load instruction to access a storage device through cache memory and to read information from the storage device; and

a specific instruction to set the existence/non-existence of writing in a specific storage area of the storage device, including a target access area of the load instruction as a monitor start trigger.

19. An information processing device which accesses information of a storage device through cache memory, comprising:

a first function to detect an instruction string composed of at least one of a first instruction to collectively read and update information in a target address or address range of the storage device and a second instruction to read information about the address or address range; and

a second function to monitor whether there is an update access to the address or address range from another processor and also to enter the information processing device into a suspense status, using detection of the instruction string as a trigger; and

a third function to release the suspense status using the occurrence of the update access to the address or address range from another processor as a trigger.

20. Cache memory which is inserted between an instruction control unit and a storage device and temporarily stores information transmitted/received between the storage device and the instruction control unit, comprising

a writing detection function to detect a possibility that information may be written into the specific storage area of the storage device, including a target access area of a load instruction to read the information from the storage device into the instruction control unit.

21. The cache memory according to claim 20, wherein

part of cache management information for managing said cache memory comprises discrimination information for discriminating the storage area of said cache memory corresponding to the specific storage area of the storage device, and the storage area of the cache memory, to which the discrimination information is attached, is designated as the monitor target of said writing detection function.

22. The cache memory according to claim 20, wherein

said writing detection function comprises at least one register, and

a monitor address indicating the specific storage area is set in said register, and the specific storage area is monitored by comparing the monitor address with an access address to all segments of cache memory.